target-mips: fix xtlb exception for loongson
Loongson 2E and 2F use the same entry for xtlb and tlb exception, at offset 0x000. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
parent
08218b3527
commit
3fc00a7bde
@ -491,7 +491,8 @@ void do_interrupt (CPUState *env)
|
||||
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
|
||||
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
|
||||
|
||||
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
|
||||
if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
|
||||
(!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
|
||||
offset = 0x080;
|
||||
else
|
||||
#endif
|
||||
@ -507,7 +508,8 @@ void do_interrupt (CPUState *env)
|
||||
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
|
||||
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
|
||||
|
||||
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
|
||||
if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
|
||||
(!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
|
||||
offset = 0x080;
|
||||
else
|
||||
#endif
|
||||
|
Loading…
Reference in New Issue
Block a user