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target/openrisc: Implement EPH bit 

Exception Prefix High (EPH) control bit of the Supervision Register
(SR).

The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR).

If SR[EPH] is set, the vector offset is logically ORed with the offset
0xF0000000.

This means if EPH is;
 * 0 - Exceptions vectors start at EVBAR
 * 1 - Exception vectors start at EVBAR | 0xF0000000

Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Tim 'mithro' Ansell 2017-04-18 16:15:51 +10:00 committed by Stafford Horne
parent 356a2db3c6
commit 3fee028d1e
1 changed files with 3 additions and 0 deletions
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3
target/openrisc/interrupt.c
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@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
if (env->cpucfgr & CPUCFGR_EVBARP) {
vect_pc |= env->evbar;
}
if (env->sr & SR_EPH) {
vect_pc |= 0xf0000000;
}
env->pc = vect_pc;
} else {
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);