accel/tcg: Introduce tlb_set_page_full
Now that we have collected all of the page data into CPUTLBEntryFull, provide an interface to record that all in one go, instead of using 4 arguments. This interface allows CPUTLBEntryFull to be extended without having to change the number of arguments. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1095,16 +1095,16 @@ static void tlb_add_large_page(CPUArchState *env, int mmu_idx,
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env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask;
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env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask;
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}
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}
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/* Add a new TLB entry. At most one entry for a given virtual address
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/*
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* Add a new TLB entry. At most one entry for a given virtual address
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* is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
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* is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
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* supplied size is only used by tlb_flush_page.
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* supplied size is only used by tlb_flush_page.
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*
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*
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* Called from TCG-generated code, which is under an RCU read-side
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* Called from TCG-generated code, which is under an RCU read-side
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* critical section.
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* critical section.
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*/
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*/
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void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
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void tlb_set_page_full(CPUState *cpu, int mmu_idx,
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hwaddr paddr, MemTxAttrs attrs, int prot,
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target_ulong vaddr, CPUTLBEntryFull *full)
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int mmu_idx, target_ulong size)
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{
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{
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CPUArchState *env = cpu->env_ptr;
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CPUArchState *env = cpu->env_ptr;
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CPUTLB *tlb = env_tlb(env);
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CPUTLB *tlb = env_tlb(env);
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@ -1117,35 +1117,36 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
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CPUTLBEntry *te, tn;
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CPUTLBEntry *te, tn;
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hwaddr iotlb, xlat, sz, paddr_page;
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hwaddr iotlb, xlat, sz, paddr_page;
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target_ulong vaddr_page;
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target_ulong vaddr_page;
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int asidx = cpu_asidx_from_attrs(cpu, attrs);
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int asidx, wp_flags, prot;
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int wp_flags;
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bool is_ram, is_romd;
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bool is_ram, is_romd;
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assert_cpu_is_self(cpu);
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assert_cpu_is_self(cpu);
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if (size <= TARGET_PAGE_SIZE) {
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if (full->lg_page_size <= TARGET_PAGE_BITS) {
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sz = TARGET_PAGE_SIZE;
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sz = TARGET_PAGE_SIZE;
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} else {
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} else {
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tlb_add_large_page(env, mmu_idx, vaddr, size);
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sz = (hwaddr)1 << full->lg_page_size;
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sz = size;
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tlb_add_large_page(env, mmu_idx, vaddr, sz);
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}
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}
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vaddr_page = vaddr & TARGET_PAGE_MASK;
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vaddr_page = vaddr & TARGET_PAGE_MASK;
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paddr_page = paddr & TARGET_PAGE_MASK;
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paddr_page = full->phys_addr & TARGET_PAGE_MASK;
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prot = full->prot;
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asidx = cpu_asidx_from_attrs(cpu, full->attrs);
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section = address_space_translate_for_iotlb(cpu, asidx, paddr_page,
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section = address_space_translate_for_iotlb(cpu, asidx, paddr_page,
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&xlat, &sz, attrs, &prot);
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&xlat, &sz, full->attrs, &prot);
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assert(sz >= TARGET_PAGE_SIZE);
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assert(sz >= TARGET_PAGE_SIZE);
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tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
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tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
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" prot=%x idx=%d\n",
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" prot=%x idx=%d\n",
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vaddr, paddr, prot, mmu_idx);
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vaddr, full->phys_addr, prot, mmu_idx);
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address = vaddr_page;
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address = vaddr_page;
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if (size < TARGET_PAGE_SIZE) {
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if (full->lg_page_size < TARGET_PAGE_BITS) {
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/* Repeat the MMU check and TLB fill on every access. */
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/* Repeat the MMU check and TLB fill on every access. */
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address |= TLB_INVALID_MASK;
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address |= TLB_INVALID_MASK;
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}
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}
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if (attrs.byte_swap) {
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if (full->attrs.byte_swap) {
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address |= TLB_BSWAP;
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address |= TLB_BSWAP;
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}
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}
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@ -1236,8 +1237,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
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* subtract here is that of the page base, and not the same as the
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* subtract here is that of the page base, and not the same as the
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* vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
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* vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
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*/
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*/
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desc->fulltlb[index] = *full;
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desc->fulltlb[index].xlat_section = iotlb - vaddr_page;
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desc->fulltlb[index].xlat_section = iotlb - vaddr_page;
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desc->fulltlb[index].attrs = attrs;
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desc->fulltlb[index].phys_addr = paddr_page;
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desc->fulltlb[index].prot = prot;
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/* Now calculate the new entry */
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/* Now calculate the new entry */
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tn.addend = addend - vaddr_page;
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tn.addend = addend - vaddr_page;
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@ -1272,9 +1275,21 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
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qemu_spin_unlock(&tlb->c.lock);
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qemu_spin_unlock(&tlb->c.lock);
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}
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}
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/* Add a new TLB entry, but without specifying the memory
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void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
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* transaction attributes to be used.
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hwaddr paddr, MemTxAttrs attrs, int prot,
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*/
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int mmu_idx, target_ulong size)
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{
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CPUTLBEntryFull full = {
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.phys_addr = paddr,
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.attrs = attrs,
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.prot = prot,
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.lg_page_size = ctz64(size)
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};
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assert(is_power_of_2(size));
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tlb_set_page_full(cpu, mmu_idx, vaddr, &full);
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}
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void tlb_set_page(CPUState *cpu, target_ulong vaddr,
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void tlb_set_page(CPUState *cpu, target_ulong vaddr,
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hwaddr paddr, int prot,
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hwaddr paddr, int prot,
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int mmu_idx, target_ulong size)
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int mmu_idx, target_ulong size)
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@ -148,7 +148,21 @@ typedef struct CPUTLBEntryFull {
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* + the offset within the target MemoryRegion (otherwise)
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* + the offset within the target MemoryRegion (otherwise)
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*/
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*/
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hwaddr xlat_section;
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hwaddr xlat_section;
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/*
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* @phys_addr contains the physical address in the address space
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* given by cpu_asidx_from_attrs(cpu, @attrs).
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*/
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hwaddr phys_addr;
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/* @attrs contains the memory transaction attributes for the page. */
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MemTxAttrs attrs;
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MemTxAttrs attrs;
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/* @prot contains the complete protections for the page. */
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uint8_t prot;
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/* @lg_page_size contains the log2 of the page size. */
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uint8_t lg_page_size;
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} CPUTLBEntryFull;
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} CPUTLBEntryFull;
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/*
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/*
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@ -257,6 +257,28 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
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uint16_t idxmap,
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uint16_t idxmap,
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unsigned bits);
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unsigned bits);
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/**
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* tlb_set_page_full:
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* @cpu: CPU context
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* @mmu_idx: mmu index of the tlb to modify
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* @vaddr: virtual address of the entry to add
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* @full: the details of the tlb entry
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*
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* Add an entry to @cpu tlb index @mmu_idx. All of the fields of
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* @full must be filled, except for xlat_section, and constitute
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* the complete description of the translated page.
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*
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* This is generally called by the target tlb_fill function after
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* having performed a successful page table walk to find the physical
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* address and attributes for the translation.
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*
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* At most one entry for a given virtual address is permitted. Only a
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* single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
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* used by tlb_flush_page.
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*/
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void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr,
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CPUTLBEntryFull *full);
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/**
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/**
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* tlb_set_page_with_attrs:
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* tlb_set_page_with_attrs:
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* @cpu: CPU to add this TLB entry for
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* @cpu: CPU to add this TLB entry for
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