hw/m68k/next-cube: Move mmio_ops into NeXTPC device
Move the registers handled by the mmio_ops struct into the NeXTPC device. This allows us to also move the scr1 and scr2 data fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-4-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
This commit is contained in:
Peter Maydell
Thomas Huth
parent
660bef3390
commit
4083163645
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@ -84,9 +84,6 @@ struct NeXTState {
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qemu_irq scsi_reset;
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qemu_irq *fd_irq;
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uint32_t scr1;
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uint32_t scr2;
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NextRtc rtc;
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};
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@ -99,6 +96,11 @@ struct NeXTPC {
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/* Temporary until all functionality has been moved into this device */
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NeXTState *ns;
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MemoryRegion mmiomem;
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uint32_t scr1;
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uint32_t scr2;
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};
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/* Thanks to NeXT forums for this */
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@ -121,13 +123,13 @@ static const uint8_t rtc_ram2[32] = {
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#define SCR2_RTDATA 0x4
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#define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10))
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static void nextscr2_write(NeXTState *s, uint32_t val, int size)
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static void nextscr2_write(NeXTPC *s, uint32_t val, int size)
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{
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static int led;
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static int phase;
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static uint8_t old_scr2;
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uint8_t scr2_2;
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NextRtc *rtc = &s->rtc;
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NextRtc *rtc = &s->ns->rtc;
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if (size == 4) {
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scr2_2 = (val >> 8) & 0xFF;
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@ -239,7 +241,7 @@ static void nextscr2_write(NeXTState *s, uint32_t val, int size)
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/* clear FTU */
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if (rtc->value & 0x04) {
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rtc->status = rtc->status & (~0x18);
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s->int_status = s->int_status & (~0x04);
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s->ns->int_status = s->ns->int_status & (~0x04);
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}
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}
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}
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@ -255,7 +257,7 @@ static void nextscr2_write(NeXTState *s, uint32_t val, int size)
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old_scr2 = scr2_2;
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}
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static uint32_t mmio_readb(NeXTState *s, hwaddr addr)
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static uint32_t mmio_readb(NeXTPC *s, hwaddr addr)
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{
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switch (addr) {
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case 0xc000:
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@ -285,7 +287,7 @@ static uint32_t mmio_readb(NeXTState *s, hwaddr addr)
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}
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}
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static uint32_t mmio_readw(NeXTState *s, hwaddr addr)
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static uint32_t mmio_readw(NeXTPC *s, hwaddr addr)
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{
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switch (addr) {
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default:
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@ -294,16 +296,16 @@ static uint32_t mmio_readw(NeXTState *s, hwaddr addr)
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}
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}
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static uint32_t mmio_readl(NeXTState *s, hwaddr addr)
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static uint32_t mmio_readl(NeXTPC *s, hwaddr addr)
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{
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switch (addr) {
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case 0x7000:
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/* DPRINTF("Read INT status: %x\n", s->int_status); */
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return s->int_status;
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/* DPRINTF("Read INT status: %x\n", s->ns->int_status); */
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return s->ns->int_status;
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case 0x7800:
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DPRINTF("MMIO Read INT mask: %x\n", s->int_mask);
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return s->int_mask;
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DPRINTF("MMIO Read INT mask: %x\n", s->ns->int_mask);
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return s->ns->int_mask;
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case 0xc000:
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return s->scr1;
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@ -317,7 +319,7 @@ static uint32_t mmio_readl(NeXTState *s, hwaddr addr)
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}
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}
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static void mmio_writeb(NeXTState *s, hwaddr addr, uint32_t val)
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static void mmio_writeb(NeXTPC *s, hwaddr addr, uint32_t val)
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{
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switch (addr) {
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case 0xd003:
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@ -329,21 +331,21 @@ static void mmio_writeb(NeXTState *s, hwaddr addr, uint32_t val)
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}
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static void mmio_writew(NeXTState *s, hwaddr addr, uint32_t val)
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static void mmio_writew(NeXTPC *s, hwaddr addr, uint32_t val)
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{
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DPRINTF("MMIO Write W\n");
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}
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static void mmio_writel(NeXTState *s, hwaddr addr, uint32_t val)
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static void mmio_writel(NeXTPC *s, hwaddr addr, uint32_t val)
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{
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switch (addr) {
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case 0x7000:
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DPRINTF("INT Status old: %x new: %x\n", s->int_status, val);
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s->int_status = val;
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DPRINTF("INT Status old: %x new: %x\n", s->ns->int_status, val);
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s->ns->int_status = val;
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break;
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case 0x7800:
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DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, val);
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s->int_mask = val;
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DPRINTF("INT Mask old: %x new: %x\n", s->ns->int_mask, val);
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s->ns->int_mask = val;
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break;
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case 0xc000:
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DPRINTF("SCR1 Write: %x\n", val);
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@ -359,15 +361,15 @@ static void mmio_writel(NeXTState *s, hwaddr addr, uint32_t val)
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static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size)
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{
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NeXTState *ns = NEXT_MACHINE(opaque);
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NeXTPC *s = NEXT_PC(opaque);
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switch (size) {
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case 1:
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return mmio_readb(ns, addr);
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return mmio_readb(s, addr);
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case 2:
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return mmio_readw(ns, addr);
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return mmio_readw(s, addr);
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case 4:
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return mmio_readl(ns, addr);
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return mmio_readl(s, addr);
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default:
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g_assert_not_reached();
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}
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@ -376,17 +378,17 @@ static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size)
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static void mmio_writefn(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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NeXTState *ns = NEXT_MACHINE(opaque);
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NeXTPC *s = NEXT_PC(opaque);
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switch (size) {
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case 1:
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mmio_writeb(ns, addr, value);
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mmio_writeb(s, addr, value);
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break;
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case 2:
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mmio_writew(ns, addr, value);
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mmio_writew(s, addr, value);
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break;
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case 4:
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mmio_writel(ns, addr, value);
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mmio_writel(s, addr, value);
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break;
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default:
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g_assert_not_reached();
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@ -870,10 +872,23 @@ static void next_escc_init(M68kCPU *cpu)
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static void next_pc_reset(DeviceState *dev)
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{
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NeXTPC *s = NEXT_PC(dev);
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/* Set internal registers to initial values */
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/* 0x0000XX00 << vital bits */
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s->scr1 = 0x00011102;
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s->scr2 = 0x00ff0c80;
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}
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static void next_pc_realize(DeviceState *dev, Error **errp)
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{
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NeXTPC *s = NEXT_PC(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&s->mmiomem, OBJECT(s), &mmio_ops, s,
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"next.mmio", 0xD0000);
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sysbus_init_mmio(sbd, &s->mmiomem);
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}
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static void next_pc_class_init(ObjectClass *klass, void *data)
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@ -898,7 +913,6 @@ static void next_cube_init(MachineState *machine)
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M68kCPU *cpu;
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CPUM68KState *env;
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MemoryRegion *rom = g_new(MemoryRegion, 1);
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MemoryRegion *mmiomem = g_new(MemoryRegion, 1);
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MemoryRegion *scrmem = g_new(MemoryRegion, 1);
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MemoryRegion *dmamem = g_new(MemoryRegion, 1);
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MemoryRegion *bmapm1 = g_new(MemoryRegion, 1);
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@ -927,10 +941,6 @@ static void next_cube_init(MachineState *machine)
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/* Temporary while we refactor this code */
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NEXT_PC(pcdev)->ns = ns;
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/* Set internal registers to initial values */
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/* 0x0000XX00 << vital bits */
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ns->scr1 = 0x00011102;
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ns->scr2 = 0x00ff0c80;
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ns->rtc.status = 0x90;
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/* Load RTC RAM - TODO: provide possibility to load contents from file */
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@ -945,9 +955,7 @@ static void next_cube_init(MachineState *machine)
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000);
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/* MMIO */
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memory_region_init_io(mmiomem, NULL, &mmio_ops, machine, "next.mmio",
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0xD0000);
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memory_region_add_subregion(sysmem, 0x02000000, mmiomem);
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sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02000000);
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/* BMAP memory */
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memory_region_init_ram_shared_nomigrate(bmapm1, NULL, "next.bmapmem", 64,
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