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trivial patches for 2023-10-12

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Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging

trivial patches for 2023-10-12

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# gpg: Signature made Wed 11 Oct 2023 17:37:51 EDT
# gpg:                using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59
# gpg:                issuer "mjt@tls.msk.ru"
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full]
# gpg:                 aka "Michael Tokarev <mjt@corpit.ru>" [full]
# gpg:                 aka "Michael Tokarev <mjt@debian.org>" [full]
# Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D  4324 457C E0A0 8044 65C5
#      Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931  4B22 701B 4F6B 1A69 3E59

* tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu:
  cpus: Remove unused smp_cores/smp_threads declarations
  scripts/xml-preprocess: Make sure this script is invoked via the right Python
  roms: use PYTHON to invoke python
  MAINTAINERS: Add some unowned files to the SBSA-REF section
  MAINTAINERS: Add section for overall sensors
  MAINTAINERS: add standard-headers to Hosts/LINUX
  MAINTAINERS: Add the CI-related doc files to the CI section
  MAINTAINERS: Add include folder to the hw/char/ section
  MAINTAINERS: Add unowned RISC-V related files to the right sections
  MAINTAINERS: Add g364fb and ds1225y to the Jazz section
  Fix compilation when UFFDIO_REGISTER is not set.
  Update AMD memory encryption document links.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-10-12 10:24:06 -04:00
commit 40886c4cf5
6 changed files with 28 additions and 13 deletions
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24
MAINTAINERS
View File

@ -318,8 +318,11 @@ R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
L: qemu-riscv@nongnu.org
S: Supported
F: configs/targets/riscv*
F: docs/system/target-riscv.rst
F: target/riscv/
F: hw/riscv/
F: hw/intc/riscv*
F: include/hw/riscv/
F: linux-user/host/riscv32/
F: linux-user/host/riscv64/
@ -331,6 +334,7 @@ L: qemu-riscv@nongnu.org
S: Supported
F: target/riscv/insn_trans/trans_xthead.c.inc
F: target/riscv/xthead*.decode
F: disas/riscv-xthead*
RISC-V XVentanaCondOps extension
M: Philipp Tomsich <philipp.tomsich@vrull.eu>
@ -338,6 +342,7 @@ L: qemu-riscv@nongnu.org
S: Maintained
F: target/riscv/XVentanaCondOps.decode
F: target/riscv/insn_trans/trans_xventanacondops.c.inc
F: disas/riscv-xventana*
RENESAS RX CPUs
R: Yoshinori Sato <ysato@users.sourceforge.jp>
@ -557,6 +562,7 @@ M: Cornelia Huck <cohuck@redhat.com>
M: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: linux-headers/
F: include/standard-headers/
F: scripts/update-linux-headers.sh
POSIX
@ -939,6 +945,9 @@ R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
L: qemu-arm@nongnu.org
S: Maintained
F: hw/arm/sbsa-ref.c
F: hw/misc/sbsa_ec.c
F: hw/watchdog/sbsa_gwdt.c
F: include/hw/watchdog/sbsa_gwdt.h
F: docs/system/arm/sbsa.rst
F: tests/avocado/machine_aarch64_sbsaref.py
@ -1286,8 +1295,10 @@ M: Hervé Poussineau <hpoussin@reactos.org>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Maintained
F: hw/mips/jazz.c
F: hw/display/g364fb.c
F: hw/display/jazz_led.c
F: hw/dma/rc4030.c
F: hw/nvram/ds1225y.c
Malta
M: Philippe Mathieu-Daudé <philmd@linaro.org>
@ -1525,6 +1536,7 @@ Microchip PolarFire SoC Icicle Kit
M: Bin Meng <bin.meng@windriver.com>
L: qemu-riscv@nongnu.org
S: Supported
F: docs/system/riscv/microchip-icicle-kit.rst
F: hw/riscv/microchip_pfsoc.c
F: hw/char/mchp_pfsoc_mmuart.c
F: hw/misc/mchp_pfsoc_dmc.c
@ -1540,6 +1552,7 @@ Shakti C class SoC
M: Vijai Kumar K <vijai@behindbytes.com>
L: qemu-riscv@nongnu.org
S: Supported
F: docs/system/riscv/shakti-c.rst
F: hw/riscv/shakti_c.c
F: hw/char/shakti_uart.c
F: include/hw/riscv/shakti_c.h
@ -1551,6 +1564,7 @@ M: Bin Meng <bin.meng@windriver.com>
M: Palmer Dabbelt <palmer@dabbelt.com>
L: qemu-riscv@nongnu.org
S: Supported
F: docs/system/riscv/sifive_u.rst
F: hw/*/*sifive*.c
F: include/hw/*/*sifive*.h
@ -1978,6 +1992,7 @@ M: Marc-André Lureau <marcandre.lureau@redhat.com>
R: Paolo Bonzini <pbonzini@redhat.com>
S: Odd Fixes
F: hw/char/
F: include/hw/char/
Network devices
M: Jason Wang <jasowang@redhat.com>
@ -3406,6 +3421,12 @@ M: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
S: Maintained
F: contrib/elf2dmp/
Overall sensors
M: Philippe Mathieu-Daudé <philmd@linaro.org>
S: Odd Fixes
F: hw/sensor
F: include/hw/sensor
I2C and SMBus
M: Corey Minyard <cminyard@mvista.com>
S: Maintained
@ -3571,7 +3592,7 @@ M: Alistair Francis <Alistair.Francis@wdc.com>
L: qemu-riscv@nongnu.org
S: Maintained
F: tcg/riscv/
F: disas/riscv.c
F: disas/riscv.[ch]
S390 TCG target
M: Richard Henderson <richard.henderson@linaro.org>
@ -3907,6 +3928,7 @@ F: .github/workflows/lockdown.yml
F: .gitlab-ci.yml
F: .gitlab-ci.d/
F: .travis.yml
F: docs/devel/ci*
F: scripts/ci/
F: tests/docker/
F: tests/vm/

6
docs/system/i386/amd-memory-encryption.rst
View File

@ -183,13 +183,13 @@ References
----------
`AMD Memory Encryption whitepaper
<https://developer.amd.com/wordpress/media/2013/12/AMD_Memory_Encryption_Whitepaper_v7-Public.pdf>`_
<https://www.amd.com/content/dam/amd/en/documents/epyc-business-docs/white-papers/memory-encryption-white-paper.pdf>`_
.. [SEVAPI] `Secure Encrypted Virtualization API
<https://www.amd.com/system/files/TechDocs/55766_SEV-KM_API_Specification.pdf>`_
.. [APMVOL2] `AMD64 Architecture Programmer's Manual Volume 2: System Programming
<https://www.amd.com/system/files/TechDocs/24593.pdf>`_
<https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf>`_
KVM Forum slides:
@ -199,7 +199,7 @@ KVM Forum slides:
<https://www.linux-kvm.org/images/9/94/Extending-Secure-Encrypted-Virtualization-with-SEV-ES-Thomas-Lendacky-AMD.pdf>`_
`AMD64 Architecture Programmer's Manual:
<http://support.amd.com/TechDocs/24593.pdf>`_
<https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf>`_
* SME is section 7.10
* SEV is section 15.34

7
include/sysemu/cpus.h
View File

@ -50,11 +50,4 @@ void cpu_synchronize_all_post_reset(void);
void cpu_synchronize_all_post_init(void);
void cpu_synchronize_all_pre_loadvm(void);
#ifndef CONFIG_USER_ONLY
/* vl.c */
/* *-user doesn't have configurable SMP topology */
extern int smp_cores;
extern int smp_threads;
#endif
#endif

2
roms/Makefile
View File

@ -147,7 +147,7 @@ skiboot:
cp skiboot/skiboot.lid ../pc-bios/skiboot.lid
efi:
python3 edk2-build.py --config edk2-build.config \
$(PYTHON) edk2-build.py --config edk2-build.config \
--version-override "edk2-stable202302-for-qemu" \
--release-date "03/01/2023"
rm -f ../pc-bios/edk2-*.fd.bz2

0
scripts/xml-preprocess.py Executable file → Normal file
View File

2
subprojects/libvhost-user/libvhost-user.c
View File

@ -631,9 +631,9 @@ static bool
generate_faults(VuDev *dev) {
unsigned int i;
for (i = 0; i < dev->nregions; i++) {
#ifdef UFFDIO_REGISTER
VuDevRegion *dev_region = &dev->regions[i];
int ret;
#ifdef UFFDIO_REGISTER
struct uffdio_register reg_struct;
/*