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target/riscv: Fix FCLASS_D being treated as RV64 only

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Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Bastian Koppelmann 2018-11-08 13:06:27 +01:00 committed by Palmer Dabbelt
parent 632fb2792b
commit 40cf6a54c9
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GPG Key ID: EF4CA1502CCBAB41
1 changed files with 3 additions and 1 deletions
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target/riscv/translate.c
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@ -1237,13 +1237,14 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
tcg_temp_free(t0); tcg_temp_free(t0);
break; break;
#if defined(TARGET_RISCV64)
case OPC_RISC_FMV_X_D: case OPC_RISC_FMV_X_D:
/* also OPC_RISC_FCLASS_D */ /* also OPC_RISC_FCLASS_D */
switch (rm) { switch (rm) {
#if defined(TARGET_RISCV64)
case 0: /* FMV */ case 0: /* FMV */
gen_set_gpr(rd, cpu_fpr[rs1]); gen_set_gpr(rd, cpu_fpr[rs1]);
break; break;
#endif
case 1: case 1:
t0 = tcg_temp_new(); t0 = tcg_temp_new();
gen_helper_fclass_d(t0, cpu_fpr[rs1]); gen_helper_fclass_d(t0, cpu_fpr[rs1]);
@ -1255,6 +1256,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
} }
break; break;
#if defined(TARGET_RISCV64)
case OPC_RISC_FMV_D_X: case OPC_RISC_FMV_D_X:
t0 = tcg_temp_new(); t0 = tcg_temp_new();
gen_get_gpr(t0, rs1); gen_get_gpr(t0, rs1);