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target-mips: check CP0 enabled for CACHE instruction also in R6

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Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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Leon Alrae 2016-03-25 13:49:35 +00:00
parent 25a611e3e4
commit 40d48212f9
1 changed files with 1 additions and 0 deletions
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target-mips/translate.c
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@ -17194,6 +17194,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
/* Treat as NOP. */
break;
case R6_OPC_CACHE:
check_cp0_enabled(ctx);
/* Treat as NOP. */
break;
case R6_OPC_SC: