target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()
The A32/T32 gen_intermediate_code_internal() is complicated because it has to deal with: * conditionally executed instructions * Thumb IT blocks * kernel helper page * M profile exception-exit special casing None of these apply to A64, so putting the "this is A64 so call the A64 decoder" check in the middle of the A32/T32 loop is confusing and means the A64 decoder's handling of things like conditional jump and singlestepping has to take account of the conditional-execution jumps the main loop might emit. Refactor the code to give A64 its own gen_intermediate_code_internal function instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Peter Maydell
parent
013424d436
commit
40f860cd6c
@ -28,6 +28,8 @@
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#include "translate.h"
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#include "qemu/host-utils.h"
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#include "exec/gen-icount.h"
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#include "helper.h"
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#define GEN_HELPER 1
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#include "helper.h"
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@ -106,7 +108,42 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp)
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{
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gen_a64_set_pc_im(s->pc - offset);
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gen_exception(excp);
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s->is_jmp = DISAS_EXC;
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}
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static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
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{
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/* No direct tb linking with singlestep or deterministic io */
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if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {
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return false;
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}
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/* Only link tbs from inside the same guest page */
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if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
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return false;
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}
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return true;
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}
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static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
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{
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TranslationBlock *tb;
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tb = s->tb;
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if (use_goto_tb(s, n, dest)) {
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tcg_gen_goto_tb(n);
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gen_a64_set_pc_im(dest);
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tcg_gen_exit_tb((tcg_target_long)tb + n);
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s->is_jmp = DISAS_TB_JUMP;
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} else {
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gen_a64_set_pc_im(dest);
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if (s->singlestep_enabled) {
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gen_exception(EXCP_DEBUG);
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}
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tcg_gen_exit_tb(0);
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s->is_jmp = DISAS_JUMP;
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}
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}
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static void real_unallocated_encoding(DisasContext *s)
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@ -120,7 +157,7 @@ static void real_unallocated_encoding(DisasContext *s)
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real_unallocated_encoding(s); \
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} while (0)
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void disas_a64_insn(CPUARMState *env, DisasContext *s)
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static void disas_a64_insn(CPUARMState *env, DisasContext *s)
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{
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uint32_t insn;
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@ -133,9 +170,171 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
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unallocated_encoding(s);
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break;
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}
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}
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if (unlikely(s->singlestep_enabled) && (s->is_jmp == DISAS_TB_JUMP)) {
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/* go through the main loop for single step */
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s->is_jmp = DISAS_JUMP;
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void gen_intermediate_code_internal_a64(ARMCPU *cpu,
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TranslationBlock *tb,
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bool search_pc)
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{
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CPUState *cs = CPU(cpu);
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CPUARMState *env = &cpu->env;
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DisasContext dc1, *dc = &dc1;
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CPUBreakpoint *bp;
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uint16_t *gen_opc_end;
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int j, lj;
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target_ulong pc_start;
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target_ulong next_page_start;
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int num_insns;
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int max_insns;
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pc_start = tb->pc;
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dc->tb = tb;
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gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
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dc->is_jmp = DISAS_NEXT;
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dc->pc = pc_start;
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dc->singlestep_enabled = cs->singlestep_enabled;
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dc->condjmp = 0;
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dc->aarch64 = 1;
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dc->thumb = 0;
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dc->bswap_code = 0;
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dc->condexec_mask = 0;
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dc->condexec_cond = 0;
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#if !defined(CONFIG_USER_ONLY)
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dc->user = 0;
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#endif
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dc->vfp_enabled = 0;
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dc->vec_len = 0;
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dc->vec_stride = 0;
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next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
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lj = -1;
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num_insns = 0;
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max_insns = tb->cflags & CF_COUNT_MASK;
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if (max_insns == 0) {
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max_insns = CF_COUNT_MASK;
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}
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gen_tb_start();
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tcg_clear_temp_count();
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do {
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if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
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QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
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if (bp->pc == dc->pc) {
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gen_exception_insn(dc, 0, EXCP_DEBUG);
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/* Advance PC so that clearing the breakpoint will
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invalidate this TB. */
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dc->pc += 2;
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goto done_generating;
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}
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}
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}
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if (search_pc) {
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j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
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if (lj < j) {
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lj++;
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while (lj < j) {
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tcg_ctx.gen_opc_instr_start[lj++] = 0;
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}
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}
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tcg_ctx.gen_opc_pc[lj] = dc->pc;
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tcg_ctx.gen_opc_instr_start[lj] = 1;
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
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tcg_gen_debug_insn_start(dc->pc);
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}
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disas_a64_insn(env, dc);
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if (tcg_check_temp_count()) {
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fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
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dc->pc);
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}
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/* Translation stops when a conditional branch is encountered.
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* Otherwise the subsequent code could get translated several times.
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* Also stop translation when a page boundary is reached. This
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* ensures prefetch aborts occur at the right place.
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*/
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num_insns++;
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} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
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!cs->singlestep_enabled &&
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!singlestep &&
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dc->pc < next_page_start &&
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num_insns < max_insns);
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if (tb->cflags & CF_LAST_IO) {
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gen_io_end();
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}
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if (unlikely(cs->singlestep_enabled) && dc->is_jmp != DISAS_EXC) {
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/* Note that this means single stepping WFI doesn't halt the CPU.
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* For conditional branch insns this is harmless unreachable code as
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* gen_goto_tb() has already handled emitting the debug exception
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* (and thus a tb-jump is not possible when singlestepping).
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*/
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assert(dc->is_jmp != DISAS_TB_JUMP);
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if (dc->is_jmp != DISAS_JUMP) {
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gen_a64_set_pc_im(dc->pc);
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}
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gen_exception(EXCP_DEBUG);
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} else {
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switch (dc->is_jmp) {
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case DISAS_NEXT:
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gen_goto_tb(dc, 1, dc->pc);
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break;
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default:
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case DISAS_JUMP:
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case DISAS_UPDATE:
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/* indicate that the hash table must be used to find the next TB */
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tcg_gen_exit_tb(0);
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break;
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case DISAS_TB_JUMP:
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case DISAS_EXC:
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case DISAS_SWI:
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break;
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case DISAS_WFI:
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/* This is a special case because we don't want to just halt the CPU
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* if trying to debug across a WFI.
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*/
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gen_helper_wfi(cpu_env);
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break;
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}
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}
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done_generating:
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gen_tb_end(tb, num_insns);
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*tcg_ctx.gen_opc_ptr = INDEX_op_end;
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#ifdef DEBUG_DISAS
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
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qemu_log("----------------\n");
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qemu_log("IN: %s\n", lookup_symbol(pc_start));
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log_target_disas(env, pc_start, dc->pc - pc_start,
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dc->thumb | (dc->bswap_code << 1));
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qemu_log("\n");
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}
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#endif
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if (search_pc) {
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j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
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lj++;
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while (lj <= j) {
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tcg_ctx.gen_opc_instr_start[lj++] = 0;
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}
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} else {
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tb->size = dc->pc - pc_start;
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tb->icount = num_insns;
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}
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}
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@ -56,11 +56,6 @@ static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
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#define IS_USER(s) (s->user)
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#endif
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/* These instructions trap after executing, so defer them until after the
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conditional execution state has been updated. */
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#define DISAS_WFI 4
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#define DISAS_SWI 5
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TCGv_ptr cpu_env;
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/* We reuse the same 64-bit temporaries for efficiency. */
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static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
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@ -900,11 +895,7 @@ DO_GEN_ST(32, MO_TEUL)
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static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
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{
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if (s->aarch64) {
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gen_a64_set_pc_im(val);
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} else {
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tcg_gen_movi_i32(cpu_R[15], val);
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}
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}
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/* Force a TB lookup after an instruction that changes the CPU state. */
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@ -10243,6 +10234,15 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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int max_insns;
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/* generate intermediate code */
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/* The A64 decoder has its own top level loop, because it doesn't need
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* the A32/T32 complexity to do with conditional execution/IT blocks/etc.
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*/
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if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
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gen_intermediate_code_internal_a64(cpu, tb, search_pc);
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return;
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}
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pc_start = tb->pc;
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dc->tb = tb;
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@ -10254,19 +10254,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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dc->singlestep_enabled = cs->singlestep_enabled;
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dc->condjmp = 0;
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if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
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dc->aarch64 = 1;
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dc->thumb = 0;
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dc->bswap_code = 0;
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dc->condexec_mask = 0;
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dc->condexec_cond = 0;
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#if !defined(CONFIG_USER_ONLY)
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dc->user = 0;
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#endif
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dc->vfp_enabled = 0;
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dc->vec_len = 0;
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dc->vec_stride = 0;
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} else {
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dc->aarch64 = 0;
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dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
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dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
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@ -10278,7 +10265,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
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dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
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dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
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}
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cpu_F0s = tcg_temp_new_i32();
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cpu_F1s = tcg_temp_new_i32();
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cpu_F0d = tcg_temp_new_i64();
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@ -10340,7 +10327,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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do {
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#ifdef CONFIG_USER_ONLY
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/* Intercept jump to the magic kernel page. */
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if (!dc->aarch64 && dc->pc >= 0xffff0000) {
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if (dc->pc >= 0xffff0000) {
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/* We always get here via a jump, so know we are not in a
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conditional execution block. */
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gen_exception(EXCP_KERNEL_TRAP);
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@ -10388,9 +10375,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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tcg_gen_debug_insn_start(dc->pc);
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}
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if (dc->aarch64) {
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disas_a64_insn(env, dc);
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} else if (dc->thumb) {
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if (dc->thumb) {
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disas_thumb_insn(env, dc);
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if (dc->condexec_mask) {
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dc->condexec_cond = (dc->condexec_cond & 0xe)
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@ -10585,8 +10570,9 @@ void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, int pc_pos)
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{
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if (is_a64(env)) {
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env->pc = tcg_ctx.gen_opc_pc[pc_pos];
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env->condexec_bits = 0;
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} else {
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env->regs[15] = tcg_ctx.gen_opc_pc[pc_pos];
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}
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env->condexec_bits = gen_opc_condexec_bits[pc_pos];
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}
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}
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@ -28,16 +28,32 @@ typedef struct DisasContext {
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extern TCGv_ptr cpu_env;
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/* target-specific extra values for is_jmp */
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/* These instructions trap after executing, so the A32/T32 decoder must
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* defer them until after the conditional execution state has been updated.
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* WFI also needs special handling when single-stepping.
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*/
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#define DISAS_WFI 4
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#define DISAS_SWI 5
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/* For instructions which unconditionally cause an exception we can skip
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* emitting unreachable code at the end of the TB in the A64 decoder
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*/
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#define DISAS_EXC 6
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#ifdef TARGET_AARCH64
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void a64_translate_init(void);
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void disas_a64_insn(CPUARMState *env, DisasContext *s);
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void gen_intermediate_code_internal_a64(ARMCPU *cpu,
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TranslationBlock *tb,
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bool search_pc);
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void gen_a64_set_pc_im(uint64_t val);
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#else
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static inline void a64_translate_init(void)
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{
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}
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static inline void disas_a64_insn(CPUARMState *env, DisasContext *s)
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static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
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TranslationBlock *tb,
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bool search_pc)
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{
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}
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