target-arm: Fix aarch64 vec_reg_offset
Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used for a big-endian host doesn't do what's intended. Fix this by adding in the vfp.regs offset after computing the inter-register offset. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1481085020-2614-2-git-send-email-rth@twiddle.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -527,7 +527,7 @@ static inline void assert_fp_access_checked(DisasContext *s)
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static inline int vec_reg_offset(DisasContext *s, int regno,
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static inline int vec_reg_offset(DisasContext *s, int regno,
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int element, TCGMemOp size)
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int element, TCGMemOp size)
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{
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{
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int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
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int offs = 0;
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#ifdef HOST_WORDS_BIGENDIAN
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#ifdef HOST_WORDS_BIGENDIAN
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/* This is complicated slightly because vfp.regs[2n] is
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/* This is complicated slightly because vfp.regs[2n] is
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* still the low half and vfp.regs[2n+1] the high half
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* still the low half and vfp.regs[2n+1] the high half
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@ -540,6 +540,7 @@ static inline int vec_reg_offset(DisasContext *s, int regno,
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#else
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#else
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offs += element * (1 << size);
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offs += element * (1 << size);
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#endif
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#endif
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offs += offsetof(CPUARMState, vfp.regs[regno * 2]);
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assert_fp_access_checked(s);
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assert_fp_access_checked(s);
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return offs;
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return offs;
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}
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}
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