From 571a7e34f956e0c7ce7fc26b31977be944a3dd94 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Fri, 7 Dec 2018 15:58:39 -0800 Subject: [PATCH 01/40] target/xtensa/import_core.sh: don't add duplicate 'static' xtensa-modules.c produced by recent Tensilica tools have Opcode_*_encode_fns arrays defined as static. Don't add extra 'static' in front of them when importing. Signed-off-by: Max Filippov --- target/xtensa/import_core.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/xtensa/import_core.sh b/target/xtensa/import_core.sh index 039406bf28..e4a2e39f63 100755 --- a/target/xtensa/import_core.sh +++ b/target/xtensa/import_core.sh @@ -27,7 +27,7 @@ tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \ # Fix up known issues in the xtensa-modules.c # tar -xf "$OVERLAY" -O binutils/xtensa-modules.c | \ - sed -e 's/\(xtensa_opcode_encode_fn.*\[\] =\)/static \1/' \ + sed -e 's/^\(xtensa_opcode_encode_fn.*\[\] =\)/static \1/' \ -e '/^int num_bypass_groups()/,/}/d' \ -e '/^int num_bypass_group_chunks()/,/}/d' \ -e '/^uint32 \*bypass_entry(int i)/,/}/d' \ From fe7869d69caeb0d77b75d14051a6e72a6a10aa76 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sat, 9 Feb 2019 18:30:00 -0800 Subject: [PATCH 02/40] target/xtensa: don't specify windowed registers manually Use libisa to extract whether opcode uses windowed registers and construct mask based on that. This only leaves special case for the 'entry' opcode, as it needs to probe a register dynamically. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 2 +- target/xtensa/helper.c | 1 + target/xtensa/translate.c | 493 +------------------------------------- 3 files changed, 12 insertions(+), 484 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index b665bfc006..f186124472 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -380,7 +380,6 @@ typedef struct XtensaOpcodeOps { XtensaOpcodeUintTest test_overflow; const uint32_t *par; uint32_t op_flags; - uint32_t windowed_register_op; uint32_t coprocessor; } XtensaOpcodeOps; @@ -438,6 +437,7 @@ struct XtensaConfig { xtensa_isa isa; XtensaOpcodeOps **opcode_ops; const XtensaOpcodeTranslators **opcode_translators; + xtensa_regfile a_regfile; uint32_t clock_freq_khz; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index bcf2f20d48..6cf1dbb8a6 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -88,6 +88,7 @@ static void init_libisa(XtensaConfig *config) #endif config->opcode_ops[i] = ops; } + config->a_regfile = xtensa_regfile_lookup(config->isa, "AR"); } void xtensa_finalize_config(XtensaConfig *config) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index d1e9f59b31..6e4f0ad44c 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -916,6 +916,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) opnds = xtensa_opcode_num_operands(isa, opc); for (opnd = vopnd = 0; opnd < opnds; ++opnd) { + if (xtensa_operand_is_register(isa, opc, opnd) && + xtensa_operand_regfile(isa, opc, opnd) == + dc->config->a_regfile) { + uint32_t v; + + xtensa_operand_get_field(isa, opc, opnd, fmt, slot, + dc->slotbuf, &v); + xtensa_operand_decode(isa, opc, opnd, &v); + windowed_register |= 1u << v; + } if (xtensa_operand_is_visible(isa, opc, opnd)) { uint32_t v; @@ -952,16 +962,6 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) if (ops->test_overflow) { windowed_register |= ops->test_overflow(dc, arg, ops->par); } - if (ops->windowed_register_op) { - uint32_t reg_opnd = ops->windowed_register_op; - - while (reg_opnd) { - unsigned i = ctz32(reg_opnd); - - windowed_register |= 1 << arg[i]; - reg_opnd ^= 1 << i; - } - } coprocessor |= ops->coprocessor; } @@ -1474,12 +1474,6 @@ static void translate_call0(DisasContext *dc, const uint32_t arg[], gen_jumpi(dc, arg[0], 0); } -static uint32_t test_overflow_callw(DisasContext *dc, const uint32_t arg[], - const uint32_t par[]) -{ - return 1 << (par[0] * 4); -} - static void translate_callw(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { @@ -2435,42 +2429,33 @@ static const XtensaOpcodeOps core_ops[] = { { .name = "abs", .translate = translate_abs, - .windowed_register_op = 0x3, }, { .name = "add", .translate = translate_add, - .windowed_register_op = 0x7, }, { .name = "add.n", .translate = translate_add, - .windowed_register_op = 0x7, }, { .name = "addi", .translate = translate_addi, - .windowed_register_op = 0x3, }, { .name = "addi.n", .translate = translate_addi, - .windowed_register_op = 0x3, }, { .name = "addmi", .translate = translate_addi, - .windowed_register_op = 0x3, }, { .name = "addx2", .translate = translate_addx, .par = (const uint32_t[]){1}, - .windowed_register_op = 0x7, }, { .name = "addx4", .translate = translate_addx, .par = (const uint32_t[]){2}, - .windowed_register_op = 0x7, }, { .name = "addx8", .translate = translate_addx, .par = (const uint32_t[]){3}, - .windowed_register_op = 0x7, }, { .name = "all4", .translate = translate_all, @@ -2482,7 +2467,6 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "and", .translate = translate_and, - .windowed_register_op = 0x7, }, { .name = "andb", .translate = translate_boolean, @@ -2503,52 +2487,42 @@ static const XtensaOpcodeOps core_ops[] = { .name = "ball", .translate = translate_ball, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x3, }, { .name = "bany", .translate = translate_bany, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x3, }, { .name = "bbc", .translate = translate_bb, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x3, }, { .name = "bbci", .translate = translate_bbi, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x1, }, { .name = "bbs", .translate = translate_bb, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x3, }, { .name = "bbsi", .translate = translate_bbi, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x1, }, { .name = "beq", .translate = translate_b, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x3, }, { .name = "beqi", .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x1, }, { .name = "beqz", .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x1, }, { .name = "beqz.n", .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x1, }, { .name = "bf", .translate = translate_bp, @@ -2557,82 +2531,66 @@ static const XtensaOpcodeOps core_ops[] = { .name = "bge", .translate = translate_b, .par = (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op = 0x3, }, { .name = "bgei", .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op = 0x1, }, { .name = "bgeu", .translate = translate_b, .par = (const uint32_t[]){TCG_COND_GEU}, - .windowed_register_op = 0x3, }, { .name = "bgeui", .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_GEU}, - .windowed_register_op = 0x1, }, { .name = "bgez", .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op = 0x1, }, { .name = "blt", .translate = translate_b, .par = (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op = 0x3, }, { .name = "blti", .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op = 0x1, }, { .name = "bltu", .translate = translate_b, .par = (const uint32_t[]){TCG_COND_LTU}, - .windowed_register_op = 0x3, }, { .name = "bltui", .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_LTU}, - .windowed_register_op = 0x1, }, { .name = "bltz", .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op = 0x1, }, { .name = "bnall", .translate = translate_ball, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x3, }, { .name = "bne", .translate = translate_b, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x3, }, { .name = "bnei", .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x1, }, { .name = "bnez", .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x1, }, { .name = "bnez.n", .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x1, }, { .name = "bnone", .translate = translate_bany, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x3, }, { .name = "break", .translate = translate_nop, @@ -2653,114 +2611,88 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "call12", .translate = translate_callw, - .test_overflow = test_overflow_callw, .par = (const uint32_t[]){3}, }, { .name = "call4", .translate = translate_callw, - .test_overflow = test_overflow_callw, .par = (const uint32_t[]){1}, }, { .name = "call8", .translate = translate_callw, - .test_overflow = test_overflow_callw, .par = (const uint32_t[]){2}, }, { .name = "callx0", .translate = translate_callx0, - .windowed_register_op = 0x1, }, { .name = "callx12", .translate = translate_callxw, - .test_overflow = test_overflow_callw, .par = (const uint32_t[]){3}, - .windowed_register_op = 0x1, }, { .name = "callx4", .translate = translate_callxw, - .test_overflow = test_overflow_callw, .par = (const uint32_t[]){1}, - .windowed_register_op = 0x1, }, { .name = "callx8", .translate = translate_callxw, - .test_overflow = test_overflow_callw, .par = (const uint32_t[]){2}, - .windowed_register_op = 0x1, }, { .name = "clamps", .translate = translate_clamps, - .windowed_register_op = 0x3, }, { .name = "clrb_expstate", .translate = translate_clrb_expstate, }, { .name = "const16", .translate = translate_const16, - .windowed_register_op = 0x1, }, { .name = "depbits", .translate = translate_depbits, - .windowed_register_op = 0x3, }, { .name = "dhi", .translate = translate_dcache, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "dhu", .translate = translate_dcache, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "dhwb", .translate = translate_dcache, - .windowed_register_op = 0x1, }, { .name = "dhwbi", .translate = translate_dcache, - .windowed_register_op = 0x1, }, { .name = "dii", .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "diu", .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "diwb", .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "diwbi", .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "dpfl", .translate = translate_dcache, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "dpfr", .translate = translate_nop, - .windowed_register_op = 0x1, }, { .name = "dpfro", .translate = translate_nop, - .windowed_register_op = 0x1, }, { .name = "dpfw", .translate = translate_nop, - .windowed_register_op = 0x1, }, { .name = "dpfwo", .translate = translate_nop, - .windowed_register_op = 0x1, }, { .name = "dsync", .translate = translate_nop, @@ -2779,7 +2711,6 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "extui", .translate = translate_extui, - .windowed_register_op = 0x3, }, { .name = "extw", .translate = translate_memw, @@ -2794,32 +2725,26 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_itlb, .par = (const uint32_t[]){true}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "ihi", .translate = translate_icache, - .windowed_register_op = 0x1, }, { .name = "ihu", .translate = translate_icache, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "iii", .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "iitlb", .translate = translate_itlb, .par = (const uint32_t[]){false}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "iiu", .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "ill", .op_flags = XTENSA_OP_ILL, @@ -2829,12 +2754,10 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "ipf", .translate = translate_nop, - .windowed_register_op = 0x1, }, { .name = "ipfl", .translate = translate_icache, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "isync", .translate = translate_nop, @@ -2844,56 +2767,45 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "jx", .translate = translate_jx, - .windowed_register_op = 0x1, }, { .name = "l16si", .translate = translate_ldst, .par = (const uint32_t[]){MO_TESW, false, false}, - .windowed_register_op = 0x3, }, { .name = "l16ui", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUW, false, false}, - .windowed_register_op = 0x3, }, { .name = "l32ai", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, true, false}, - .windowed_register_op = 0x3, }, { .name = "l32e", .translate = translate_l32e, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "l32i", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, false, false}, - .windowed_register_op = 0x3, }, { .name = "l32i.n", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, false, false}, - .windowed_register_op = 0x3, }, { .name = "l32r", .translate = translate_l32r, - .windowed_register_op = 0x1, }, { .name = "l8ui", .translate = translate_ldst, .par = (const uint32_t[]){MO_UB, false, false}, - .windowed_register_op = 0x3, }, { .name = "lddec", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_NONE, 0, 0, -4}, - .windowed_register_op = 0x2, }, { .name = "ldinc", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_NONE, 0, 0, 4}, - .windowed_register_op = 0x2, }, { .name = "ldpte", .op_flags = XTENSA_OP_ILL, @@ -2901,147 +2813,117 @@ static const XtensaOpcodeOps core_ops[] = { .name = "loop", .translate = translate_loop, .par = (const uint32_t[]){TCG_COND_NEVER}, - .windowed_register_op = 0x1, }, { .name = "loopgtz", .translate = translate_loop, .par = (const uint32_t[]){TCG_COND_GT}, - .windowed_register_op = 0x1, }, { .name = "loopnez", .translate = translate_loop, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x1, }, { .name = "max", .translate = translate_smax, - .windowed_register_op = 0x7, }, { .name = "maxu", .translate = translate_umax, - .windowed_register_op = 0x7, }, { .name = "memw", .translate = translate_memw, }, { .name = "min", .translate = translate_smin, - .windowed_register_op = 0x7, }, { .name = "minu", .translate = translate_umin, - .windowed_register_op = 0x7, }, { .name = "mov", .translate = translate_mov, - .windowed_register_op = 0x3, }, { .name = "mov.n", .translate = translate_mov, - .windowed_register_op = 0x3, }, { .name = "moveqz", .translate = translate_movcond, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x7, }, { .name = "movf", .translate = translate_movp, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x3, }, { .name = "movgez", .translate = translate_movcond, .par = (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op = 0x7, }, { .name = "movi", .translate = translate_movi, - .windowed_register_op = 0x1, }, { .name = "movi.n", .translate = translate_movi, - .windowed_register_op = 0x1, }, { .name = "movltz", .translate = translate_movcond, .par = (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op = 0x7, }, { .name = "movnez", .translate = translate_movcond, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x7, }, { .name = "movsp", .translate = translate_movsp, - .windowed_register_op = 0x3, .op_flags = XTENSA_OP_ALLOCA, }, { .name = "movt", .translate = translate_movp, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x3, }, { .name = "mul.aa.hh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HH, 0}, - .windowed_register_op = 0x3, }, { .name = "mul.aa.hl", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HL, 0}, - .windowed_register_op = 0x3, }, { .name = "mul.aa.lh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LH, 0}, - .windowed_register_op = 0x3, }, { .name = "mul.aa.ll", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LL, 0}, - .windowed_register_op = 0x3, }, { .name = "mul.ad.hh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HH, 0}, - .windowed_register_op = 0x1, }, { .name = "mul.ad.hl", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HL, 0}, - .windowed_register_op = 0x1, }, { .name = "mul.ad.lh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LH, 0}, - .windowed_register_op = 0x1, }, { .name = "mul.ad.ll", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LL, 0}, - .windowed_register_op = 0x1, }, { .name = "mul.da.hh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HH, 0}, - .windowed_register_op = 0x2, }, { .name = "mul.da.hl", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HL, 0}, - .windowed_register_op = 0x2, }, { .name = "mul.da.lh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LH, 0}, - .windowed_register_op = 0x2, }, { .name = "mul.da.ll", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LL, 0}, - .windowed_register_op = 0x2, }, { .name = "mul.dd.hh", .translate = translate_mac16, @@ -3062,112 +2944,90 @@ static const XtensaOpcodeOps core_ops[] = { .name = "mul16s", .translate = translate_mul16, .par = (const uint32_t[]){true}, - .windowed_register_op = 0x7, }, { .name = "mul16u", .translate = translate_mul16, .par = (const uint32_t[]){false}, - .windowed_register_op = 0x7, }, { .name = "mula.aa.hh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HH, 0}, - .windowed_register_op = 0x3, }, { .name = "mula.aa.hl", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HL, 0}, - .windowed_register_op = 0x3, }, { .name = "mula.aa.lh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LH, 0}, - .windowed_register_op = 0x3, }, { .name = "mula.aa.ll", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LL, 0}, - .windowed_register_op = 0x3, }, { .name = "mula.ad.hh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HH, 0}, - .windowed_register_op = 0x1, }, { .name = "mula.ad.hl", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HL, 0}, - .windowed_register_op = 0x1, }, { .name = "mula.ad.lh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LH, 0}, - .windowed_register_op = 0x1, }, { .name = "mula.ad.ll", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LL, 0}, - .windowed_register_op = 0x1, }, { .name = "mula.da.hh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 0}, - .windowed_register_op = 0x2, }, { .name = "mula.da.hh.lddec", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, -4}, - .windowed_register_op = 0xa, }, { .name = "mula.da.hh.ldinc", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 4}, - .windowed_register_op = 0xa, }, { .name = "mula.da.hl", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 0}, - .windowed_register_op = 0x2, }, { .name = "mula.da.hl.lddec", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, -4}, - .windowed_register_op = 0xa, }, { .name = "mula.da.hl.ldinc", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 4}, - .windowed_register_op = 0xa, }, { .name = "mula.da.lh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 0}, - .windowed_register_op = 0x2, }, { .name = "mula.da.lh.lddec", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, -4}, - .windowed_register_op = 0xa, }, { .name = "mula.da.lh.ldinc", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 4}, - .windowed_register_op = 0xa, }, { .name = "mula.da.ll", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 0}, - .windowed_register_op = 0x2, }, { .name = "mula.da.ll.lddec", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, -4}, - .windowed_register_op = 0xa, }, { .name = "mula.da.ll.ldinc", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 4}, - .windowed_register_op = 0xa, }, { .name = "mula.dd.hh", .translate = translate_mac16, @@ -3176,12 +3036,10 @@ static const XtensaOpcodeOps core_ops[] = { .name = "mula.dd.hh.lddec", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, -4}, - .windowed_register_op = 0x2, }, { .name = "mula.dd.hh.ldinc", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 4}, - .windowed_register_op = 0x2, }, { .name = "mula.dd.hl", .translate = translate_mac16, @@ -3190,12 +3048,10 @@ static const XtensaOpcodeOps core_ops[] = { .name = "mula.dd.hl.lddec", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, -4}, - .windowed_register_op = 0x2, }, { .name = "mula.dd.hl.ldinc", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 4}, - .windowed_register_op = 0x2, }, { .name = "mula.dd.lh", .translate = translate_mac16, @@ -3204,12 +3060,10 @@ static const XtensaOpcodeOps core_ops[] = { .name = "mula.dd.lh.lddec", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, -4}, - .windowed_register_op = 0x2, }, { .name = "mula.dd.lh.ldinc", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 4}, - .windowed_register_op = 0x2, }, { .name = "mula.dd.ll", .translate = translate_mac16, @@ -3218,76 +3072,61 @@ static const XtensaOpcodeOps core_ops[] = { .name = "mula.dd.ll.lddec", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, -4}, - .windowed_register_op = 0x2, }, { .name = "mula.dd.ll.ldinc", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 4}, - .windowed_register_op = 0x2, }, { .name = "mull", .translate = translate_mull, - .windowed_register_op = 0x7, }, { .name = "muls.aa.hh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HH, 0}, - .windowed_register_op = 0x3, }, { .name = "muls.aa.hl", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HL, 0}, - .windowed_register_op = 0x3, }, { .name = "muls.aa.lh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LH, 0}, - .windowed_register_op = 0x3, }, { .name = "muls.aa.ll", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LL, 0}, - .windowed_register_op = 0x3, }, { .name = "muls.ad.hh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HH, 0}, - .windowed_register_op = 0x1, }, { .name = "muls.ad.hl", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HL, 0}, - .windowed_register_op = 0x1, }, { .name = "muls.ad.lh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LH, 0}, - .windowed_register_op = 0x1, }, { .name = "muls.ad.ll", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LL, 0}, - .windowed_register_op = 0x1, }, { .name = "muls.da.hh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HH, 0}, - .windowed_register_op = 0x2, }, { .name = "muls.da.hl", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HL, 0}, - .windowed_register_op = 0x2, }, { .name = "muls.da.lh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LH, 0}, - .windowed_register_op = 0x2, }, { .name = "muls.da.ll", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LL, 0}, - .windowed_register_op = 0x2, }, { .name = "muls.dd.hh", .translate = translate_mac16, @@ -3308,16 +3147,13 @@ static const XtensaOpcodeOps core_ops[] = { .name = "mulsh", .translate = translate_mulh, .par = (const uint32_t[]){true}, - .windowed_register_op = 0x7, }, { .name = "muluh", .translate = translate_mulh, .par = (const uint32_t[]){false}, - .windowed_register_op = 0x7, }, { .name = "neg", .translate = translate_neg, - .windowed_register_op = 0x3, }, { .name = "nop", .translate = translate_nop, @@ -3327,15 +3163,12 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "nsa", .translate = translate_nsa, - .windowed_register_op = 0x3, }, { .name = "nsau", .translate = translate_nsau, - .windowed_register_op = 0x3, }, { .name = "or", .translate = translate_or, - .windowed_register_op = 0x7, }, { .name = "orb", .translate = translate_boolean, @@ -3349,56 +3182,46 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_ptlb, .par = (const uint32_t[]){true}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "pitlb", .translate = translate_ptlb, .par = (const uint32_t[]){false}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "quos", .translate = translate_quos, .par = (const uint32_t[]){true}, .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, - .windowed_register_op = 0x7, }, { .name = "quou", .translate = translate_quou, .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, - .windowed_register_op = 0x7, }, { .name = "rdtlb0", .translate = translate_rtlb, .par = (const uint32_t[]){true, 0}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "rdtlb1", .translate = translate_rtlb, .par = (const uint32_t[]){true, 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "read_impwire", .translate = translate_read_impwire, - .windowed_register_op = 0x1, }, { .name = "rems", .translate = translate_quos, .par = (const uint32_t[]){false}, .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, - .windowed_register_op = 0x7, }, { .name = "remu", .translate = translate_remu, .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, - .windowed_register_op = 0x7, }, { .name = "rer", .translate = translate_rer, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "ret", .translate = translate_ret, @@ -3448,13 +3271,11 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_rtlb, .par = (const uint32_t[]){false, 0}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "ritlb1", .translate = translate_rtlb, .par = (const uint32_t[]){false, 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "rotw", .translate = translate_rotw, @@ -3466,526 +3287,449 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "rsr.176", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){176}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.208", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){208}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.acchi", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){ACCHI}, - .windowed_register_op = 0x1, }, { .name = "rsr.acclo", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){ACCLO}, - .windowed_register_op = 0x1, }, { .name = "rsr.atomctl", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){ATOMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.br", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){BR}, - .windowed_register_op = 0x1, }, { .name = "rsr.cacheattr", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CACHEATTR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ccompare0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CCOMPARE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ccompare1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CCOMPARE + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ccompare2", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CCOMPARE + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ccount", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CCOUNT}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "rsr.configid0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CONFIGID0}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.configid1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CONFIGID1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.cpenable", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CPENABLE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.dbreaka0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DBREAKA}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.dbreaka1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DBREAKA + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.dbreakc0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DBREAKC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.dbreakc1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DBREAKC + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ddr", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.debugcause", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DEBUGCAUSE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.depc", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DEPC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.dtlbcfg", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DTLBCFG}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc2", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc3", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc4", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc5", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc6", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc7", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1 + 6}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.eps2", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPS2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.eps3", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPS2 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.eps4", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPS2 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.eps5", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPS2 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.eps6", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPS2 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.eps7", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPS2 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.exccause", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCCAUSE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave2", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave3", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave4", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave5", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave6", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave7", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1 + 6}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excvaddr", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCVADDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ibreaka0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){IBREAKA}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ibreaka1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){IBREAKA + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ibreakenable", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){IBREAKENABLE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.icount", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){ICOUNT}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.icountlevel", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){ICOUNTLEVEL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.intclear", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){INTCLEAR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.intenable", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){INTENABLE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.interrupt", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){INTSET}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "rsr.intset", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){INTSET}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "rsr.itlbcfg", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){ITLBCFG}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.lbeg", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){LBEG}, - .windowed_register_op = 0x1, }, { .name = "rsr.lcount", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){LCOUNT}, - .windowed_register_op = 0x1, }, { .name = "rsr.lend", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){LEND}, - .windowed_register_op = 0x1, }, { .name = "rsr.litbase", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){LITBASE}, - .windowed_register_op = 0x1, }, { .name = "rsr.m0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MR}, - .windowed_register_op = 0x1, }, { .name = "rsr.m1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MR + 1}, - .windowed_register_op = 0x1, }, { .name = "rsr.m2", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MR + 2}, - .windowed_register_op = 0x1, }, { .name = "rsr.m3", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MR + 3}, - .windowed_register_op = 0x1, }, { .name = "rsr.memctl", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MEMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.misc0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MISC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.misc1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MISC + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.misc2", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MISC + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.misc3", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MISC + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.prid", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){PRID}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ps", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){PS}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ptevaddr", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){PTEVADDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.rasid", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){RASID}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.sar", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){SAR}, - .windowed_register_op = 0x1, }, { .name = "rsr.scompare1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){SCOMPARE1}, - .windowed_register_op = 0x1, }, { .name = "rsr.vecbase", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){VECBASE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.windowbase", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){WINDOW_BASE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.windowstart", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){WINDOW_START}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsync", .translate = translate_nop, @@ -3993,80 +3737,65 @@ static const XtensaOpcodeOps core_ops[] = { .name = "rur.expstate", .translate = translate_rur, .par = (const uint32_t[]){EXPSTATE}, - .windowed_register_op = 0x1, }, { .name = "rur.fcr", .translate = translate_rur, .par = (const uint32_t[]){FCR}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "rur.fsr", .translate = translate_rur, .par = (const uint32_t[]){FSR}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "rur.threadptr", .translate = translate_rur, .par = (const uint32_t[]){THREADPTR}, - .windowed_register_op = 0x1, }, { .name = "s16i", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUW, false, true}, - .windowed_register_op = 0x3, }, { .name = "s32c1i", .translate = translate_s32c1i, - .windowed_register_op = 0x3, }, { .name = "s32e", .translate = translate_s32e, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "s32i", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, false, true}, - .windowed_register_op = 0x3, }, { .name = "s32i.n", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, false, true}, - .windowed_register_op = 0x3, }, { .name = "s32nb", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, false, true}, - .windowed_register_op = 0x3, }, { .name = "s32ri", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, true, true}, - .windowed_register_op = 0x3, }, { .name = "s8i", .translate = translate_ldst, .par = (const uint32_t[]){MO_UB, false, true}, - .windowed_register_op = 0x3, }, { .name = "salt", .translate = translate_salt, .par = (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op = 0x7, }, { .name = "saltu", .translate = translate_salt, .par = (const uint32_t[]){TCG_COND_LTU}, - .windowed_register_op = 0x7, }, { .name = "setb_expstate", .translate = translate_setb_expstate, }, { .name = "sext", .translate = translate_sext, - .windowed_register_op = 0x3, }, { .name = "simcall", .translate = translate_simcall, @@ -4075,69 +3804,54 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "sll", .translate = translate_sll, - .windowed_register_op = 0x3, }, { .name = "slli", .translate = translate_slli, - .windowed_register_op = 0x3, }, { .name = "sra", .translate = translate_sra, - .windowed_register_op = 0x3, }, { .name = "srai", .translate = translate_srai, - .windowed_register_op = 0x3, }, { .name = "src", .translate = translate_src, - .windowed_register_op = 0x7, }, { .name = "srl", .translate = translate_srl, - .windowed_register_op = 0x3, }, { .name = "srli", .translate = translate_srli, - .windowed_register_op = 0x3, }, { .name = "ssa8b", .translate = translate_ssa8b, - .windowed_register_op = 0x1, }, { .name = "ssa8l", .translate = translate_ssa8l, - .windowed_register_op = 0x1, }, { .name = "ssai", .translate = translate_ssai, }, { .name = "ssl", .translate = translate_ssl, - .windowed_register_op = 0x1, }, { .name = "ssr", .translate = translate_ssr, - .windowed_register_op = 0x1, }, { .name = "sub", .translate = translate_sub, - .windowed_register_op = 0x7, }, { .name = "subx2", .translate = translate_subx, .par = (const uint32_t[]){1}, - .windowed_register_op = 0x7, }, { .name = "subx4", .translate = translate_subx, .par = (const uint32_t[]){2}, - .windowed_register_op = 0x7, }, { .name = "subx8", .translate = translate_subx, .par = (const uint32_t[]){3}, - .windowed_register_op = 0x7, }, { .name = "syscall", .op_flags = XTENSA_OP_SYSCALL, @@ -4145,22 +3859,18 @@ static const XtensaOpcodeOps core_ops[] = { .name = "umul.aa.hh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HH, 0}, - .windowed_register_op = 0x3, }, { .name = "umul.aa.hl", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HL, 0}, - .windowed_register_op = 0x3, }, { .name = "umul.aa.lh", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LH, 0}, - .windowed_register_op = 0x3, }, { .name = "umul.aa.ll", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LL, 0}, - .windowed_register_op = 0x3, }, { .name = "waiti", .translate = translate_waiti, @@ -4170,362 +3880,309 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_wtlb, .par = (const uint32_t[]){true}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x3, }, { .name = "wer", .translate = translate_wer, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "witlb", .translate = translate_wtlb, .par = (const uint32_t[]){false}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x3, }, { .name = "wrmsk_expstate", .translate = translate_wrmsk_expstate, - .windowed_register_op = 0x3, }, { .name = "wsr.176", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){176}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.208", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){208}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.acchi", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){ACCHI}, - .windowed_register_op = 0x1, }, { .name = "wsr.acclo", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){ACCLO}, - .windowed_register_op = 0x1, }, { .name = "wsr.atomctl", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){ATOMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.br", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){BR}, - .windowed_register_op = 0x1, }, { .name = "wsr.cacheattr", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CACHEATTR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.ccompare0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CCOMPARE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.ccompare1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CCOMPARE + 1}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.ccompare2", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CCOMPARE + 2}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.ccount", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CCOUNT}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.configid0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CONFIGID0}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.configid1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CONFIGID1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.cpenable", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CPENABLE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.dbreaka0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DBREAKA}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.dbreaka1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DBREAKA + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.dbreakc0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DBREAKC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.dbreakc1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DBREAKC + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.ddr", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.debugcause", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DEBUGCAUSE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.depc", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DEPC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.dtlbcfg", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DTLBCFG}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc2", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc3", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc4", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc5", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc6", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc7", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1 + 6}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.eps2", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPS2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.eps3", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPS2 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.eps4", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPS2 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.eps5", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPS2 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.eps6", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPS2 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.eps7", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPS2 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.exccause", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCCAUSE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave2", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave3", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave4", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave5", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave6", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave7", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1 + 6}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excvaddr", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCVADDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.ibreaka0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){IBREAKA}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.ibreaka1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){IBREAKA + 1}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.ibreakenable", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){IBREAKENABLE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.icount", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){ICOUNT}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.icountlevel", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){ICOUNTLEVEL}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.intclear", .translate = translate_wsr, @@ -4535,7 +4192,6 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "wsr.intenable", .translate = translate_wsr, @@ -4545,7 +4201,6 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "wsr.interrupt", .translate = translate_wsr, @@ -4555,7 +4210,6 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "wsr.intset", .translate = translate_wsr, @@ -4565,114 +4219,97 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "wsr.itlbcfg", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){ITLBCFG}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.lbeg", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){LBEG}, .op_flags = XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.lcount", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){LCOUNT}, - .windowed_register_op = 0x1, }, { .name = "wsr.lend", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){LEND}, .op_flags = XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.litbase", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){LITBASE}, .op_flags = XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.m0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MR}, - .windowed_register_op = 0x1, }, { .name = "wsr.m1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MR + 1}, - .windowed_register_op = 0x1, }, { .name = "wsr.m2", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MR + 2}, - .windowed_register_op = 0x1, }, { .name = "wsr.m3", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MR + 3}, - .windowed_register_op = 0x1, }, { .name = "wsr.memctl", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MEMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.misc0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MISC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.misc1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MISC + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.misc2", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MISC + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.misc3", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MISC + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.mmid", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MMID}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.prid", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){PRID}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.ps", .translate = translate_wsr, @@ -4682,80 +4319,67 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "wsr.ptevaddr", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){PTEVADDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.rasid", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){RASID}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.sar", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){SAR}, - .windowed_register_op = 0x1, }, { .name = "wsr.scompare1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){SCOMPARE1}, - .windowed_register_op = 0x1, }, { .name = "wsr.vecbase", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){VECBASE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.windowbase", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){WINDOW_BASE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.windowstart", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){WINDOW_START}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wur.expstate", .translate = translate_wur, .par = (const uint32_t[]){EXPSTATE}, - .windowed_register_op = 0x1, }, { .name = "wur.fcr", .translate = translate_wur, .par = (const uint32_t[]){FCR}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "wur.fsr", .translate = translate_wur, .par = (const uint32_t[]){FSR}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "wur.threadptr", .translate = translate_wur, .par = (const uint32_t[]){THREADPTR}, - .windowed_register_op = 0x1, }, { .name = "xor", .translate = translate_xor, - .windowed_register_op = 0x7, }, { .name = "xorb", .translate = translate_boolean, @@ -4766,340 +4390,291 @@ static const XtensaOpcodeOps core_ops[] = { .test_ill = test_ill_xsr, .par = (const uint32_t[]){176}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.208", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){208}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.acchi", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){ACCHI}, - .windowed_register_op = 0x1, }, { .name = "xsr.acclo", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){ACCLO}, - .windowed_register_op = 0x1, }, { .name = "xsr.atomctl", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){ATOMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.br", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){BR}, - .windowed_register_op = 0x1, }, { .name = "xsr.cacheattr", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CACHEATTR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.ccompare0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CCOMPARE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.ccompare1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CCOMPARE + 1}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.ccompare2", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CCOMPARE + 2}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.ccount", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CCOUNT}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.configid0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CONFIGID0}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.configid1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CONFIGID1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.cpenable", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CPENABLE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.dbreaka0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DBREAKA}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.dbreaka1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DBREAKA + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.dbreakc0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DBREAKC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.dbreakc1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DBREAKC + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.ddr", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.debugcause", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DEBUGCAUSE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.depc", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DEPC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.dtlbcfg", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DTLBCFG}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc2", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc3", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc4", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc5", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc6", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc7", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1 + 6}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.eps2", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPS2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.eps3", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPS2 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.eps4", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPS2 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.eps5", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPS2 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.eps6", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPS2 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.eps7", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPS2 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.exccause", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCCAUSE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave2", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave3", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave4", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave5", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave6", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave7", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1 + 6}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excvaddr", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCVADDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.ibreaka0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){IBREAKA}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.ibreaka1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){IBREAKA + 1}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.ibreakenable", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){IBREAKENABLE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.icount", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){ICOUNT}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.icountlevel", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){ICOUNTLEVEL}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.intclear", .translate = translate_xsr, @@ -5109,7 +4684,6 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "xsr.intenable", .translate = translate_xsr, @@ -5119,7 +4693,6 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "xsr.interrupt", .translate = translate_xsr, @@ -5129,7 +4702,6 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "xsr.intset", .translate = translate_xsr, @@ -5139,107 +4711,91 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "xsr.itlbcfg", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){ITLBCFG}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.lbeg", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){LBEG}, .op_flags = XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.lcount", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){LCOUNT}, - .windowed_register_op = 0x1, }, { .name = "xsr.lend", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){LEND}, .op_flags = XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.litbase", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){LITBASE}, .op_flags = XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.m0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MR}, - .windowed_register_op = 0x1, }, { .name = "xsr.m1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MR + 1}, - .windowed_register_op = 0x1, }, { .name = "xsr.m2", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MR + 2}, - .windowed_register_op = 0x1, }, { .name = "xsr.m3", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MR + 3}, - .windowed_register_op = 0x1, }, { .name = "xsr.memctl", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MEMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.misc0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MISC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.misc1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MISC + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.misc2", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MISC + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.misc3", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MISC + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.prid", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){PRID}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.ps", .translate = translate_xsr, @@ -5249,54 +4805,46 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "xsr.ptevaddr", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){PTEVADDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.rasid", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){RASID}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.sar", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){SAR}, - .windowed_register_op = 0x1, }, { .name = "xsr.scompare1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){SCOMPARE1}, - .windowed_register_op = 0x1, }, { .name = "xsr.vecbase", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){VECBASE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.windowbase", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){WINDOW_BASE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.windowstart", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){WINDOW_START}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, }; @@ -5504,43 +5052,36 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "ceil.s", .translate = translate_ftoi_s, .par = (const uint32_t[]){float_round_up, false}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "float.s", .translate = translate_float_s, .par = (const uint32_t[]){false}, - .windowed_register_op = 0x2, .coprocessor = 0x1, }, { .name = "floor.s", .translate = translate_ftoi_s, .par = (const uint32_t[]){float_round_down, false}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "lsi", .translate = translate_ldsti, .par = (const uint32_t[]){false, false}, - .windowed_register_op = 0x2, .coprocessor = 0x1, }, { .name = "lsiu", .translate = translate_ldsti, .par = (const uint32_t[]){false, true}, - .windowed_register_op = 0x2, .coprocessor = 0x1, }, { .name = "lsx", .translate = translate_ldstx, .par = (const uint32_t[]){false, false}, - .windowed_register_op = 0x6, .coprocessor = 0x1, }, { .name = "lsxu", .translate = translate_ldstx, .par = (const uint32_t[]){false, true}, - .windowed_register_op = 0x6, .coprocessor = 0x1, }, { .name = "madd.s", @@ -5554,7 +5095,6 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "moveqz.s", .translate = translate_movcond_s, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x4, .coprocessor = 0x1, }, { .name = "movf.s", @@ -5565,19 +5105,16 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "movgez.s", .translate = translate_movcond_s, .par = (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op = 0x4, .coprocessor = 0x1, }, { .name = "movltz.s", .translate = translate_movcond_s, .par = (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op = 0x4, .coprocessor = 0x1, }, { .name = "movnez.s", .translate = translate_movcond_s, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x4, .coprocessor = 0x1, }, { .name = "movt.s", @@ -5614,37 +5151,31 @@ static const XtensaOpcodeOps fpu2000_ops[] = { }, { .name = "rfr", .translate = translate_rfr_s, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "round.s", .translate = translate_ftoi_s, .par = (const uint32_t[]){float_round_nearest_even, false}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "ssi", .translate = translate_ldsti, .par = (const uint32_t[]){true, false}, - .windowed_register_op = 0x2, .coprocessor = 0x1, }, { .name = "ssiu", .translate = translate_ldsti, .par = (const uint32_t[]){true, true}, - .windowed_register_op = 0x2, .coprocessor = 0x1, }, { .name = "ssx", .translate = translate_ldstx, .par = (const uint32_t[]){true, false}, - .windowed_register_op = 0x6, .coprocessor = 0x1, }, { .name = "ssxu", .translate = translate_ldstx, .par = (const uint32_t[]){true, true}, - .windowed_register_op = 0x6, .coprocessor = 0x1, }, { .name = "sub.s", @@ -5654,7 +5185,6 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "trunc.s", .translate = translate_ftoi_s, .par = (const uint32_t[]){float_round_to_zero, false}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "ueq.s", @@ -5665,7 +5195,6 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "ufloat.s", .translate = translate_float_s, .par = (const uint32_t[]){true}, - .windowed_register_op = 0x2, .coprocessor = 0x1, }, { .name = "ule.s", @@ -5686,12 +5215,10 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "utrunc.s", .translate = translate_ftoi_s, .par = (const uint32_t[]){float_round_to_zero, true}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "wfr", .translate = translate_wfr_s, - .windowed_register_op = 0x2, .coprocessor = 0x1, }, }; From 9791e7e91819468fa4009809fd340575f3fd3d12 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 11 Feb 2019 02:00:06 -0800 Subject: [PATCH 03/40] target/xtensa: get rid of gen_callw[i] Merge gen_callwi and gen_callw into their only users, translate_callw and translate_callxw. Extract jump slot adjustment logic into a separate function and use it in gen_jumpi and translate_callw. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 6e4f0ad44c..62283cd1cc 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -387,13 +387,19 @@ static void gen_jump(DisasContext *dc, TCGv dest) gen_jump_slot(dc, dest, -1); } +static int adjust_jump_slot(DisasContext *dc, uint32_t dest, int slot) +{ + if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) { + return -1; + } else { + return slot; + } +} + static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) { TCGv_i32 tmp = tcg_const_i32(dest); - if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) { - slot = -1; - } - gen_jump_slot(dc, tmp, slot); + gen_jump_slot(dc, tmp, adjust_jump_slot(dc, dest, slot)); tcg_temp_free(tmp); } @@ -410,21 +416,6 @@ static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest, gen_jump_slot(dc, dest, slot); } -static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest) -{ - gen_callw_slot(dc, callinc, dest, -1); -} - -static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot) -{ - TCGv_i32 tmp = tcg_const_i32(dest); - if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) { - slot = -1; - } - gen_callw_slot(dc, callinc, tmp, slot); - tcg_temp_free(tmp); -} - static bool gen_check_loop_end(DisasContext *dc, int slot) { if (dc->base.pc_next == dc->lend) { @@ -1477,7 +1468,9 @@ static void translate_call0(DisasContext *dc, const uint32_t arg[], static void translate_callw(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - gen_callwi(dc, par[0], arg[0], 0); + TCGv_i32 tmp = tcg_const_i32(arg[0]); + gen_callw_slot(dc, par[0], tmp, adjust_jump_slot(dc, arg[0], 0)); + tcg_temp_free(tmp); } static void translate_callx0(DisasContext *dc, const uint32_t arg[], @@ -1496,7 +1489,7 @@ static void translate_callxw(DisasContext *dc, const uint32_t arg[], TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); - gen_callw(dc, par[0], tmp); + gen_callw_slot(dc, par[0], tmp, -1); tcg_temp_free(tmp); } From 2012f47e2371537bf41a9347af6db1d3d675a1a4 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 17:52:12 -0800 Subject: [PATCH 04/40] target/xtensa: fixup test_mmuhifi_c3 overlay xtensa-modules part of the test_mmuhifi_c3 core is missing fixes that returns XTENSA_UNDEFINED for undefined opcodes and marks all data structures static. Run sed script from target/xtensa/import_core.sh on it. This fixes test_sr tests for missing special registers. Signed-off-by: Max Filippov --- .../core-test_mmuhifi_c3/xtensa-modules.inc.c | 1322 ++++++++--------- 1 file changed, 661 insertions(+), 661 deletions(-) diff --git a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c index ef70f80f1d..687631b8fb 100644 --- a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c +++ b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c @@ -24159,2627 +24159,2627 @@ Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) slotbuf[0] = 0xe7d014; } -xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { Opcode_excw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { Opcode_call12_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { Opcode_call8_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { Opcode_call4_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { Opcode_entry_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { Opcode_retw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { Opcode_call0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { Opcode_ill_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { Opcode_loop_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { Opcode_ret_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { Opcode_memw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { Opcode_extw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { Opcode_isync_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { Opcode_esync_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { Opcode_wsr_176_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { Opcode_mull_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { Opcode_break_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { Opcode_iii_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { Opcode_lict_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { Opcode_licw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { Opcode_sict_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { Opcode_dii_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { Opcode_rer_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { Opcode_wer_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0 }; @@ -30818,7 +30818,7 @@ Slot_inst_decode (const xtensa_insnbuf insn) } break; } - return 0; + return XTENSA_UNDEFINED; } static int @@ -30869,7 +30869,7 @@ Slot_inst16b_decode (const xtensa_insnbuf insn) } break; } - return 0; + return XTENSA_UNDEFINED; } static int @@ -30886,7 +30886,7 @@ Slot_inst16a_decode (const xtensa_insnbuf insn) case 11: return OPCODE_ADDI_N; } - return 0; + return XTENSA_UNDEFINED; } static int @@ -31561,7 +31561,7 @@ Slot_ae_slot0_decode (const xtensa_insnbuf insn) return OPCODE_BF; break; } - return 0; + return XTENSA_UNDEFINED; } static int @@ -32279,7 +32279,7 @@ Slot_ae_slot1_decode (const xtensa_insnbuf insn) return OPCODE_AE_MULZSSQ32SP16U_LL; break; } - return 0; + return XTENSA_UNDEFINED; } From 0e7c887919e44f25491a4eb86403e947d9d54937 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sat, 9 Feb 2019 20:43:58 -0800 Subject: [PATCH 05/40] target/xtensa: move xtensa_finalize_config to xtensa_core_class_init Don't run xtensa_finalize_config at the time of core registration, instead run it at the CPU class initialization. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 1 - target/xtensa/helper.c | 36 +++++++++++++++++++----------------- target/xtensa/overlay_tool.h | 1 - 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index f186124472..47d80a59e2 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -566,7 +566,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, void xtensa_translate_init(void); void xtensa_breakpoint_handler(CPUState *cs); -void xtensa_finalize_config(XtensaConfig *config); void xtensa_register_core(XtensaConfigList *node); void xtensa_sim_open_console(Chardev *chr); void check_interrupts(CPUXtensaState *s); diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 6cf1dbb8a6..321ca42955 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -34,22 +34,6 @@ static struct XtensaConfigList *xtensa_cores; -static void xtensa_core_class_init(ObjectClass *oc, void *data) -{ - CPUClass *cc = CPU_CLASS(oc); - XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc); - const XtensaConfig *config = data; - - xcc->config = config; - - /* Use num_core_regs to see only non-privileged registers in an unmodified - * gdb. Use num_regs to see all registers. gdb modification is required - * for that: reset bit 0 in the 'flags' field of the registers definitions - * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. - */ - cc->gdb_num_core_regs = config->gdb_regmap.num_regs; -} - static void init_libisa(XtensaConfig *config) { unsigned i, j; @@ -91,7 +75,7 @@ static void init_libisa(XtensaConfig *config) config->a_regfile = xtensa_regfile_lookup(config->isa, "AR"); } -void xtensa_finalize_config(XtensaConfig *config) +static void xtensa_finalize_config(XtensaConfig *config) { if (config->isa_internal) { init_libisa(config); @@ -112,6 +96,24 @@ void xtensa_finalize_config(XtensaConfig *config) } } +static void xtensa_core_class_init(ObjectClass *oc, void *data) +{ + CPUClass *cc = CPU_CLASS(oc); + XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc); + XtensaConfig *config = data; + + xtensa_finalize_config(config); + xcc->config = config; + + /* + * Use num_core_regs to see only non-privileged registers in an unmodified + * gdb. Use num_regs to see all registers. gdb modification is required + * for that: reset bit 0 in the 'flags' field of the registers definitions + * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. + */ + cc->gdb_num_core_regs = config->gdb_regmap.num_regs; +} + void xtensa_register_core(XtensaConfigList *node) { TypeInfo type = { diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index 12609a0d0c..ea07576bc9 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -377,7 +377,6 @@ static XtensaConfigList node = { \ .config = &core, \ }; \ - xtensa_finalize_config(&core); \ xtensa_register_core(&node); \ } #else From 759039737504c3f11098f7240c6048c6279e2215 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sat, 9 Feb 2019 23:21:44 -0800 Subject: [PATCH 06/40] target/xtensa: don't require opcode table sorting Requirement for alphabetical opcode sorting in opcode tables is awkward and does not allow sharing implementation between multiple opcodes. Use hash tables to find opcodes by name. Move implementation from the translate.c to the helper.c to its only user and remove declaration from the cpu.h Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 2 -- target/xtensa/helper.c | 42 +++++++++++++++++++++++++++++++++++++++ target/xtensa/translate.c | 14 ------------- 3 files changed, 42 insertions(+), 16 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 47d80a59e2..2765665cec 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -587,8 +587,6 @@ static inline void xtensa_select_static_vectors(CPUXtensaState *env, env->static_vectors = n; } void xtensa_runstall(CPUXtensaState *env, bool runstall); -XtensaOpcodeOps *xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, - const char *opcode); #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) #define XTENSA_OPTION_ALL (~(uint64_t)0) diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 321ca42955..57709fc20c 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -30,10 +30,52 @@ #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" +#include "qemu/error-report.h" #include "qemu/host-utils.h" static struct XtensaConfigList *xtensa_cores; +static void add_translator_to_hash(GHashTable *translator, + const char *name, + const XtensaOpcodeOps *opcode) +{ + if (!g_hash_table_insert(translator, (void *)name, (void *)opcode)) { + error_report("Multiple definitions of '%s' opcode in a single table", + name); + } +} + +static GHashTable *hash_opcode_translators(const XtensaOpcodeTranslators *t) +{ + unsigned i, j; + GHashTable *translator = g_hash_table_new(g_str_hash, g_str_equal); + + for (i = 0; i < t->num_opcodes; ++i) { + add_translator_to_hash(translator, + (void *)t->opcode[i].name, + (void *)(t->opcode + i)); + } + return translator; +} + +static XtensaOpcodeOps * +xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, + const char *name) +{ + static GHashTable *translators; + GHashTable *translator; + + if (translators == NULL) { + translators = g_hash_table_new(g_direct_hash, g_direct_equal); + } + translator = g_hash_table_lookup(translators, t); + if (translator == NULL) { + translator = hash_opcode_translators(t); + g_hash_table_insert(translators, (void *)t, translator); + } + return g_hash_table_lookup(translator, name); +} + static void init_libisa(XtensaConfig *config) { unsigned i, j; diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 62283cd1cc..26342aaa1f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1274,20 +1274,6 @@ void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, env->pc = data[0]; } -static int compare_opcode_ops(const void *a, const void *b) -{ - return strcmp((const char *)a, - ((const XtensaOpcodeOps *)b)->name); -} - -XtensaOpcodeOps * -xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, - const char *name) -{ - return bsearch(name, t->opcode, t->num_opcodes, - sizeof(XtensaOpcodeOps), compare_opcode_ops); -} - static void translate_abs(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { From d863fcf7f5b4f363e7ba2f95ce622f93dd4e866d Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sat, 9 Feb 2019 23:39:10 -0800 Subject: [PATCH 07/40] target/xtensa: allow multiple names for single opcode There are opcodes that differ only in encoding or possible range of immediate arguments. Allow multiple names for single opcode translation table entry to reduce code duplication in that case. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 4 +- target/xtensa/helper.c | 16 ++++-- target/xtensa/translate.c | 100 +++++++++++++++++--------------------- 3 files changed, 60 insertions(+), 60 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 2765665cec..db8ee70a03 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -371,10 +371,12 @@ enum { XTENSA_OP_CHECK_INTERRUPTS = 0x200, XTENSA_OP_EXIT_TB_M1 = 0x400, XTENSA_OP_EXIT_TB_0 = 0x800, + + XTENSA_OP_NAME_ARRAY = 0x8000, }; typedef struct XtensaOpcodeOps { - const char *name; + const void *name; XtensaOpcodeOp translate; XtensaOpcodeBoolTest test_ill; XtensaOpcodeUintTest test_overflow; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 57709fc20c..7008c6390d 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -51,9 +51,19 @@ static GHashTable *hash_opcode_translators(const XtensaOpcodeTranslators *t) GHashTable *translator = g_hash_table_new(g_str_hash, g_str_equal); for (i = 0; i < t->num_opcodes; ++i) { - add_translator_to_hash(translator, - (void *)t->opcode[i].name, - (void *)(t->opcode + i)); + if (t->opcode[i].op_flags & XTENSA_OP_NAME_ARRAY) { + const char * const *name = t->opcode[i].name; + + for (j = 0; name[j]; ++j) { + add_translator_to_hash(translator, + (void *)name[j], + (void *)(t->opcode + i)); + } + } else { + add_translator_to_hash(translator, + (void *)t->opcode[i].name, + (void *)(t->opcode + i)); + } } return translator; } diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 26342aaa1f..1b730781ec 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -2409,17 +2409,17 @@ static const XtensaOpcodeOps core_ops[] = { .name = "abs", .translate = translate_abs, }, { - .name = "add", + .name = (const char * const[]) { + "add", "add.n", NULL, + }, .translate = translate_add, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "add.n", - .translate = translate_add, - }, { - .name = "addi", - .translate = translate_addi, - }, { - .name = "addi.n", + .name = (const char * const[]) { + "addi", "addi.n", NULL, + }, .translate = translate_addi, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "addmi", .translate = translate_addi, @@ -2495,13 +2495,12 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_EQ}, }, { - .name = "beqz", - .translate = translate_bz, - .par = (const uint32_t[]){TCG_COND_EQ}, - }, { - .name = "beqz.n", + .name = (const char * const[]) { + "beqz", "beqz.n", NULL, + }, .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_EQ}, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "bf", .translate = translate_bp, @@ -2559,13 +2558,12 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_NE}, }, { - .name = "bnez", - .translate = translate_bz, - .par = (const uint32_t[]){TCG_COND_NE}, - }, { - .name = "bnez.n", + .name = (const char * const[]) { + "bnez", "bnez.n", NULL, + }, .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_NE}, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "bnone", .translate = translate_bany, @@ -2725,11 +2723,10 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, }, { - .name = "ill", - .op_flags = XTENSA_OP_ILL, - }, { - .name = "ill.n", - .op_flags = XTENSA_OP_ILL, + .name = (const char * const[]) { + "ill", "ill.n", NULL, + }, + .op_flags = XTENSA_OP_ILL | XTENSA_OP_NAME_ARRAY, }, { .name = "ipf", .translate = translate_nop, @@ -2763,13 +2760,12 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_l32e, .op_flags = XTENSA_OP_PRIVILEGED, }, { - .name = "l32i", - .translate = translate_ldst, - .par = (const uint32_t[]){MO_TEUL, false, false}, - }, { - .name = "l32i.n", + .name = (const char * const[]) { + "l32i", "l32i.n", NULL, + }, .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, false, false}, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "l32r", .translate = translate_l32r, @@ -2816,11 +2812,11 @@ static const XtensaOpcodeOps core_ops[] = { .name = "minu", .translate = translate_umin, }, { - .name = "mov", - .translate = translate_mov, - }, { - .name = "mov.n", + .name = (const char * const[]) { + "mov", "mov.n", NULL, + }, .translate = translate_mov, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "moveqz", .translate = translate_movcond, @@ -3134,11 +3130,11 @@ static const XtensaOpcodeOps core_ops[] = { .name = "neg", .translate = translate_neg, }, { - .name = "nop", - .translate = translate_nop, - }, { - .name = "nop.n", + .name = (const char * const[]) { + "nop", "nop.n", NULL, + }, .translate = translate_nop, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "nsa", .translate = translate_nsa, @@ -3202,21 +3198,18 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_rer, .op_flags = XTENSA_OP_PRIVILEGED, }, { - .name = "ret", + .name = (const char * const[]) { + "ret", "ret.n", NULL, + }, .translate = translate_ret, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "ret.n", - .translate = translate_ret, - }, { - .name = "retw", + .name = (const char * const[]) { + "retw", "retw.n", NULL, + }, .translate = translate_retw, .test_ill = test_ill_retw, - .op_flags = XTENSA_OP_UNDERFLOW, - }, { - .name = "retw.n", - .translate = translate_retw, - .test_ill = test_ill_retw, - .op_flags = XTENSA_OP_UNDERFLOW, + .op_flags = XTENSA_OP_UNDERFLOW | XTENSA_OP_NAME_ARRAY, }, { .name = "rfdd", .op_flags = XTENSA_OP_ILL, @@ -3742,17 +3735,12 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_s32e, .op_flags = XTENSA_OP_PRIVILEGED, }, { - .name = "s32i", - .translate = translate_ldst, - .par = (const uint32_t[]){MO_TEUL, false, true}, - }, { - .name = "s32i.n", - .translate = translate_ldst, - .par = (const uint32_t[]){MO_TEUL, false, true}, - }, { - .name = "s32nb", + .name = (const char * const[]) { + "s32i", "s32i.n", "s32nb", NULL, + }, .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, false, true}, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "s32ri", .translate = translate_ldst, From fa6bc73c8b46782bf07dadcac908405cf19b8ab8 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Tue, 2 Oct 2018 18:50:13 -0700 Subject: [PATCH 08/40] target/xtensa: implement wide branches and loops FLIX adds branch and loop instruction variants with 15- and 18-bit wide target offset. Implement them as additional names for the ordinary branch/loop opcodes. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 243 +++++++++++++++++++++++++------------- 1 file changed, 159 insertions(+), 84 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 1b730781ec..e8dddd32b3 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -2463,40 +2463,64 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_all, .par = (const uint32_t[]){false, 8}, }, { - .name = "ball", + .name = (const char * const[]) { + "ball", "ball.w15", "ball.w18", NULL, + }, .translate = translate_ball, .par = (const uint32_t[]){TCG_COND_EQ}, - }, { - .name = "bany", - .translate = translate_bany, - .par = (const uint32_t[]){TCG_COND_NE}, - }, { - .name = "bbc", - .translate = translate_bb, - .par = (const uint32_t[]){TCG_COND_EQ}, - }, { - .name = "bbci", - .translate = translate_bbi, - .par = (const uint32_t[]){TCG_COND_EQ}, - }, { - .name = "bbs", - .translate = translate_bb, - .par = (const uint32_t[]){TCG_COND_NE}, - }, { - .name = "bbsi", - .translate = translate_bbi, - .par = (const uint32_t[]){TCG_COND_NE}, - }, { - .name = "beq", - .translate = translate_b, - .par = (const uint32_t[]){TCG_COND_EQ}, - }, { - .name = "beqi", - .translate = translate_bi, - .par = (const uint32_t[]){TCG_COND_EQ}, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = (const char * const[]) { - "beqz", "beqz.n", NULL, + "bany", "bany.w15", "bany.w18", NULL, + }, + .translate = translate_bany, + .par = (const uint32_t[]){TCG_COND_NE}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bbc", "bbc.w15", "bbc.w18", NULL, + }, + .translate = translate_bb, + .par = (const uint32_t[]){TCG_COND_EQ}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bbci", "bbci.w15", "bbci.w18", NULL, + }, + .translate = translate_bbi, + .par = (const uint32_t[]){TCG_COND_EQ}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bbs", "bbs.w15", "bbs.w18", NULL, + }, + .translate = translate_bb, + .par = (const uint32_t[]){TCG_COND_NE}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bbsi", "bbsi.w15", "bbsi.w18", NULL, + }, + .translate = translate_bbi, + .par = (const uint32_t[]){TCG_COND_NE}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "beq", "beq.w15", "beq.w18", NULL, + }, + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_EQ}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "beqi", "beqi.w15", "beqi.w18", NULL, + }, + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_EQ}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "beqz", "beqz.n", "beqz.w15", "beqz.w18", NULL, }, .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_EQ}, @@ -2506,68 +2530,110 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_bp, .par = (const uint32_t[]){TCG_COND_EQ}, }, { - .name = "bge", + .name = (const char * const[]) { + "bge", "bge.w15", "bge.w18", NULL, + }, .translate = translate_b, .par = (const uint32_t[]){TCG_COND_GE}, - }, { - .name = "bgei", - .translate = translate_bi, - .par = (const uint32_t[]){TCG_COND_GE}, - }, { - .name = "bgeu", - .translate = translate_b, - .par = (const uint32_t[]){TCG_COND_GEU}, - }, { - .name = "bgeui", - .translate = translate_bi, - .par = (const uint32_t[]){TCG_COND_GEU}, - }, { - .name = "bgez", - .translate = translate_bz, - .par = (const uint32_t[]){TCG_COND_GE}, - }, { - .name = "blt", - .translate = translate_b, - .par = (const uint32_t[]){TCG_COND_LT}, - }, { - .name = "blti", - .translate = translate_bi, - .par = (const uint32_t[]){TCG_COND_LT}, - }, { - .name = "bltu", - .translate = translate_b, - .par = (const uint32_t[]){TCG_COND_LTU}, - }, { - .name = "bltui", - .translate = translate_bi, - .par = (const uint32_t[]){TCG_COND_LTU}, - }, { - .name = "bltz", - .translate = translate_bz, - .par = (const uint32_t[]){TCG_COND_LT}, - }, { - .name = "bnall", - .translate = translate_ball, - .par = (const uint32_t[]){TCG_COND_NE}, - }, { - .name = "bne", - .translate = translate_b, - .par = (const uint32_t[]){TCG_COND_NE}, - }, { - .name = "bnei", - .translate = translate_bi, - .par = (const uint32_t[]){TCG_COND_NE}, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = (const char * const[]) { - "bnez", "bnez.n", NULL, + "bgei", "bgei.w15", "bgei.w18", NULL, + }, + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_GE}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bgeu", "bgeu.w15", "bgeu.w18", NULL, + }, + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_GEU}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bgeui", "bgeui.w15", "bgeui.w18", NULL, + }, + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_GEU}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bgez", "bgez.w15", "bgez.w18", NULL, + }, + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_GE}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "blt", "blt.w15", "blt.w18", NULL, + }, + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_LT}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "blti", "blti.w15", "blti.w18", NULL, + }, + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_LT}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bltu", "bltu.w15", "bltu.w18", NULL, + }, + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_LTU}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bltui", "bltui.w15", "bltui.w18", NULL, + }, + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_LTU}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bltz", "bltz.w15", "bltz.w18", NULL, + }, + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_LT}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bnall", "bnall.w15", "bnall.w18", NULL, + }, + .translate = translate_ball, + .par = (const uint32_t[]){TCG_COND_NE}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bne", "bne.w15", "bne.w18", NULL, + }, + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_NE}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bnei", "bnei.w15", "bnei.w18", NULL, + }, + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_NE}, + .op_flags = XTENSA_OP_NAME_ARRAY, + }, { + .name = (const char * const[]) { + "bnez", "bnez.n", "bnez.w15", "bnez.w18", NULL, }, .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_NE}, .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bnone", + .name = (const char * const[]) { + "bnone", "bnone.w15", "bnone.w18", NULL, + }, .translate = translate_bany, .par = (const uint32_t[]){TCG_COND_EQ}, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "break", .translate = translate_nop, @@ -2785,17 +2851,26 @@ static const XtensaOpcodeOps core_ops[] = { .name = "ldpte", .op_flags = XTENSA_OP_ILL, }, { - .name = "loop", + .name = (const char * const[]) { + "loop", "loop.w15", NULL, + }, .translate = translate_loop, .par = (const uint32_t[]){TCG_COND_NEVER}, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "loopgtz", + .name = (const char * const[]) { + "loopgtz", "loopgtz.w15", NULL, + }, .translate = translate_loop, .par = (const uint32_t[]){TCG_COND_GT}, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "loopnez", + .name = (const char * const[]) { + "loopnez", "loopnez.w15", NULL, + }, .translate = translate_loop, .par = (const uint32_t[]){TCG_COND_NE}, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "max", .translate = translate_smax, From 20e9fd0fc0634de24ee2763d769e3780e369afdd Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Tue, 29 Jan 2019 19:21:10 -0800 Subject: [PATCH 09/40] target/xtensa: sort FLIX instruction opcodes Opcodes in different slots may read and write same resources (registers, states). In the absence of resource dependency loops it must be possible to sort opcodes to avoid interference. Record resources used by each opcode in the bundle. Build opcode dependency graph and use topological sort to order its nodes. In case of success translate opcodes in sort order. In case of failure report and raise invalid opcode exception. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 2 + target/xtensa/translate.c | 227 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 221 insertions(+), 8 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index db8ee70a03..c59f79e563 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -373,6 +373,8 @@ enum { XTENSA_OP_EXIT_TB_0 = 0x800, XTENSA_OP_NAME_ARRAY = 0x8000, + + XTENSA_OP_CONTROL_FLOW = 0x10000, }; typedef struct XtensaOpcodeOps { diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index e8dddd32b3..bda4e9469b 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -846,6 +846,157 @@ static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0) return xtensa_isa_length_from_chars(dc->config->isa, &op0); } +struct opcode_arg_info { + uint32_t resource; + int index; +}; + +struct slot_prop { + XtensaOpcodeOps *ops; + uint32_t arg[MAX_OPCODE_ARGS]; + uint32_t raw_arg[MAX_OPCODE_ARGS]; + struct opcode_arg_info in[MAX_OPCODE_ARGS]; + struct opcode_arg_info out[MAX_OPCODE_ARGS]; + unsigned n_in; + unsigned n_out; + uint32_t op_flags; +}; + +enum resource_type { + RES_REGFILE, + RES_STATE, + RES_MAX, +}; + +static uint32_t encode_resource(enum resource_type r, unsigned g, unsigned n) +{ + assert(r < RES_MAX && g < 256 && n < 65536); + return (r << 24) | (g << 16) | n; +} + +/* + * a depends on b if b must be executed before a, + * because a's side effects will destroy b's inputs. + */ +static bool op_depends_on(const struct slot_prop *a, + const struct slot_prop *b) +{ + unsigned i = 0; + unsigned j = 0; + + if (a->op_flags & XTENSA_OP_CONTROL_FLOW) { + return true; + } + while (i < a->n_out && j < b->n_in) { + if (a->out[i].resource < b->in[j].resource) { + ++i; + } else if (a->out[i].resource > b->in[j].resource) { + ++j; + } else { + return true; + } + } + return false; +} + +/* + * Calculate evaluation order for slot opcodes. + * Build opcode order graph and output its nodes in topological sort order. + * An edge a -> b in the graph means that opcode a must be followed by + * opcode b. + */ +static bool tsort(struct slot_prop *slot, + struct slot_prop *sorted[], + unsigned n) +{ + struct tsnode { + unsigned n_in_edge; + unsigned n_out_edge; + unsigned out_edge[MAX_INSN_SLOTS]; + } node[MAX_INSN_SLOTS]; + + unsigned in[MAX_INSN_SLOTS]; + unsigned i, j; + unsigned n_in = 0; + unsigned n_out = 0; + unsigned n_edge = 0; + unsigned in_idx; + + for (i = 0; i < n; ++i) { + node[i].n_in_edge = 0; + node[i].n_out_edge = 0; + } + + for (i = 0; i < n; ++i) { + unsigned n_out_edge = 0; + + for (j = 0; j < n; ++j) { + if (i != j && op_depends_on(slot + j, slot + i)) { + node[i].out_edge[n_out_edge] = j; + ++node[j].n_in_edge; + ++n_out_edge; + ++n_edge; + } + } + node[i].n_out_edge = n_out_edge; + } + + for (i = 0; i < n; ++i) { + if (!node[i].n_in_edge) { + in[n_in] = i; + ++n_in; + } + } + + for (in_idx = 0; in_idx < n_in; ++in_idx) { + i = in[in_idx]; + sorted[n_out] = slot + i; + ++n_out; + for (j = 0; j < node[i].n_out_edge; ++j) { + --n_edge; + if (--node[node[i].out_edge[j]].n_in_edge == 0) { + in[n_in] = node[i].out_edge[j]; + ++n_in; + } + } + } + return n_edge == 0; +} + +static void opcode_add_resource(struct slot_prop *op, + uint32_t resource, char direction, + int index) +{ + switch (direction) { + case 'm': + case 'i': + assert(op->n_in < ARRAY_SIZE(op->in)); + op->in[op->n_in].resource = resource; + op->in[op->n_in].index = index; + ++op->n_in; + /* fall through */ + case 'o': + if (direction == 'm' || direction == 'o') { + assert(op->n_out < ARRAY_SIZE(op->out)); + op->out[op->n_out].resource = resource; + op->out[op->n_out].index = index; + ++op->n_out; + } + break; + default: + g_assert_not_reached(); + } +} + +static int resource_compare(const void *a, const void *b) +{ + const struct opcode_arg_info *pa = a; + const struct opcode_arg_info *pb = b; + + return pa->resource < pb->resource ? + -1 : (pa->resource > pb->resource ? 1 : 0); +} + static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) { xtensa_isa isa = dc->config->isa; @@ -855,11 +1006,8 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) int slot, slots; unsigned i; uint32_t op_flags = 0; - struct { - XtensaOpcodeOps *ops; - uint32_t arg[MAX_OPCODE_ARGS]; - uint32_t raw_arg[MAX_OPCODE_ARGS]; - } slot_prop[MAX_INSN_SLOTS]; + struct slot_prop slot_prop[MAX_INSN_SLOTS]; + struct slot_prop *ordered[MAX_INSN_SLOTS]; uint32_t debug_cause = 0; uint32_t windowed_register = 0; uint32_t coprocessor = 0; @@ -954,6 +1102,68 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) windowed_register |= ops->test_overflow(dc, arg, ops->par); } coprocessor |= ops->coprocessor; + + if (slots > 1) { + slot_prop[slot].n_in = 0; + slot_prop[slot].n_out = 0; + slot_prop[slot].op_flags = 0; + + opnds = xtensa_opcode_num_operands(isa, opc); + + for (opnd = vopnd = 0; opnd < opnds; ++opnd) { + bool visible = xtensa_operand_is_visible(isa, opc, opnd); + + if (xtensa_operand_is_register(isa, opc, opnd)) { + xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd); + uint32_t v = 0; + + xtensa_operand_get_field(isa, opc, opnd, fmt, slot, + dc->slotbuf, &v); + xtensa_operand_decode(isa, opc, opnd, &v); + opcode_add_resource(slot_prop + slot, + encode_resource(RES_REGFILE, rf, v), + xtensa_operand_inout(isa, opc, opnd), + visible ? vopnd : -1); + } + if (visible) { + ++vopnd; + } + } + + opnds = xtensa_opcode_num_stateOperands(isa, opc); + + for (opnd = 0; opnd < opnds; ++opnd) { + xtensa_state state = xtensa_stateOperand_state(isa, opc, opnd); + + opcode_add_resource(slot_prop + slot, + encode_resource(RES_STATE, 0, state), + xtensa_stateOperand_inout(isa, opc, opnd), + -1); + } + if (xtensa_opcode_is_branch(isa, opc) || + xtensa_opcode_is_jump(isa, opc) || + xtensa_opcode_is_loop(isa, opc) || + xtensa_opcode_is_call(isa, opc)) { + slot_prop[slot].op_flags |= XTENSA_OP_CONTROL_FLOW; + } + + qsort(slot_prop[slot].in, slot_prop[slot].n_in, + sizeof(slot_prop[slot].in[0]), resource_compare); + qsort(slot_prop[slot].out, slot_prop[slot].n_out, + sizeof(slot_prop[slot].out[0]), resource_compare); + } + } + + if (slots > 1) { + if (!tsort(slot_prop, ordered, slots)) { + qemu_log_mask(LOG_UNIMP, + "Circular resource dependencies (pc = %08x)\n", + dc->pc); + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return; + } + } else { + ordered[0] = slot_prop + 0; } if ((op_flags & XTENSA_OP_PRIVILEGED) && @@ -1002,10 +1212,11 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } for (slot = 0; slot < slots; ++slot) { - XtensaOpcodeOps *ops = slot_prop[slot].ops; + struct slot_prop *pslot = ordered[slot]; + XtensaOpcodeOps *ops = pslot->ops; - dc->raw_arg = slot_prop[slot].raw_arg; - ops->translate(dc, slot_prop[slot].arg, ops->par); + dc->raw_arg = pslot->raw_arg; + ops->translate(dc, pslot->arg, ops->par); } if (dc->base.is_jmp == DISAS_NEXT) { From 45b71a795e5add347f0ba7aba526896132e9b986 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Wed, 30 Jan 2019 14:48:22 -0800 Subject: [PATCH 10/40] target/xtensa: add generic instruction post-processing Some opcodes may need additional actions at every exit from the translated instruction or may need to amend TB exit slots available to jumps generated for the instruction. Add gen_postprocess function and call it from the gen_jump_slot and from the disas_xtensa_insn. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 8 ++++++++ target/xtensa/translate.c | 33 +++++++++++++++++++++++++-------- 2 files changed, 33 insertions(+), 8 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c59f79e563..a3bab9c5a2 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -368,9 +368,17 @@ enum { XTENSA_OP_DIVIDE_BY_ZERO = 0x100, + /* Postprocessing flags */ XTENSA_OP_CHECK_INTERRUPTS = 0x200, XTENSA_OP_EXIT_TB_M1 = 0x400, XTENSA_OP_EXIT_TB_0 = 0x800, + XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000, + + XTENSA_OP_POSTPROCESS = + XTENSA_OP_CHECK_INTERRUPTS | + XTENSA_OP_EXIT_TB_M1 | + XTENSA_OP_EXIT_TB_0 | + XTENSA_OP_SYNC_REGISTER_WINDOW, XTENSA_OP_NAME_ARRAY = 0x8000, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index bda4e9469b..e7ef6a8998 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -71,6 +71,7 @@ struct DisasContext { unsigned cpenable; + uint32_t op_flags; uint32_t *raw_arg; xtensa_insnbuf insnbuf; xtensa_insnbuf slotbuf; @@ -363,6 +364,8 @@ static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask) return true; } +static int gen_postprocess(DisasContext *dc, int slot); + static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) { tcg_gen_mov_i32(cpu_pc, dest); @@ -372,6 +375,9 @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) if (dc->base.singlestep_enabled) { gen_exception(dc, EXCP_DEBUG); } else { + if (dc->op_flags & XTENSA_OP_POSTPROCESS) { + slot = gen_postprocess(dc, slot); + } if (slot >= 0) { tcg_gen_goto_tb(slot); tcg_gen_exit_tb(dc->base.tb, slot); @@ -846,6 +852,19 @@ static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0) return xtensa_isa_length_from_chars(dc->config->isa, &op0); } +static int gen_postprocess(DisasContext *dc, int slot) +{ + uint32_t op_flags = dc->op_flags; + + if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { + gen_check_interrupts(dc); + } + if (op_flags & XTENSA_OP_EXIT_TB_M1) { + slot = -1; + } + return slot; +} + struct opcode_arg_info { uint32_t resource; int index; @@ -1211,6 +1230,8 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } } + dc->op_flags = op_flags; + for (slot = 0; slot < slots; ++slot) { struct slot_prop *pslot = ordered[slot]; XtensaOpcodeOps *ops = pslot->ops; @@ -1220,21 +1241,17 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } if (dc->base.is_jmp == DISAS_NEXT) { - if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { - gen_check_interrupts(dc); - } - + gen_postprocess(dc, 0); + dc->op_flags = 0; if (op_flags & XTENSA_OP_EXIT_TB_M1) { /* Change in mmu index, memory mapping or tb->flags; exit tb */ gen_jumpi_check_loop_end(dc, -1); } else if (op_flags & XTENSA_OP_EXIT_TB_0) { gen_jumpi_check_loop_end(dc, 0); + } else { + gen_check_loop_end(dc, 0); } } - - if (dc->base.is_jmp == DISAS_NEXT) { - gen_check_loop_end(dc, 0); - } dc->pc = dc->base.pc_next; } From 8df3fd359697d68095c5f1ba47e83e8e237a3055 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Wed, 30 Jan 2019 14:56:29 -0800 Subject: [PATCH 11/40] target/xtensa: move WINDOW_BASE SR update to postprocessing Opcodes that modify WINDOW_BASE SR don't have dependency on opcodes that use windowed registers. If such opcodes are combined in a single instruction they may not be correctly ordered. Instead of adding said dependency use temporary register to store changed WINDOW_BASE value and do actual register window rotation as a postprocessing step. Not all opcodes that change WINDOW_BASE need this: retw, rfwo and rfwu are also jump opcodes, so they are guaranteed to be translated last and thus will not affect other opcodes in the same instruction. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 1 + target/xtensa/helper.h | 3 +-- target/xtensa/translate.c | 30 ++++++++++++++++++++++-------- target/xtensa/win_helper.c | 14 ++++---------- 4 files changed, 28 insertions(+), 20 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index a3bab9c5a2..dca4e4b111 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -486,6 +486,7 @@ typedef struct CPUXtensaState { float64 f64; } fregs[16]; float_status fp_status; + uint32_t windowbase_next; #ifndef CONFIG_USER_ONLY xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index 2a7db35874..b6529a8925 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -3,12 +3,11 @@ DEF_HELPER_3(exception_cause, noreturn, env, i32, i32) DEF_HELPER_4(exception_cause_vaddr, noreturn, env, i32, i32, i32) DEF_HELPER_3(debug_exception, noreturn, env, i32, i32) -DEF_HELPER_2(wsr_windowbase, void, env, i32) +DEF_HELPER_1(sync_windowbase, void, env) DEF_HELPER_4(entry, void, env, i32, i32, i32) DEF_HELPER_2(test_ill_retw, void, env, i32) DEF_HELPER_2(test_underflow_retw, void, env, i32) DEF_HELPER_2(retw, i32, env, i32) -DEF_HELPER_2(rotw, void, env, i32) DEF_HELPER_3(window_check, noreturn, env, i32, i32) DEF_HELPER_1(restore_owb, void, env) DEF_HELPER_2(movsp, void, env, i32) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index e7ef6a8998..cbb8d879a8 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -82,6 +82,7 @@ static TCGv_i32 cpu_R[16]; static TCGv_i32 cpu_FR[16]; static TCGv_i32 cpu_SR[256]; static TCGv_i32 cpu_UR[256]; +static TCGv_i32 cpu_windowbase_next; #include "exec/gen-icount.h" @@ -253,6 +254,11 @@ void xtensa_translate_init(void) uregnames[i].name); } } + + cpu_windowbase_next = + tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, windowbase_next), + "windowbase_next"); } static inline bool option_enabled(DisasContext *dc, int opt) @@ -557,7 +563,7 @@ static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s) #ifndef CONFIG_USER_ONLY static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) { - gen_helper_wsr_windowbase(cpu_env, v); + tcg_gen_mov_i32(cpu_windowbase_next, v); } static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v) @@ -859,6 +865,9 @@ static int gen_postprocess(DisasContext *dc, int slot) if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { gen_check_interrupts(dc); } + if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) { + gen_helper_sync_windowbase(cpu_env); + } if (op_flags & XTENSA_OP_EXIT_TB_M1) { slot = -1; } @@ -2268,9 +2277,7 @@ static void translate_rfw(DisasContext *dc, const uint32_t arg[], static void translate_rotw(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - TCGv_i32 tmp = tcg_const_i32(arg[0]); - gen_helper_rotw(cpu_env, tmp); - tcg_temp_free(tmp); + tcg_gen_addi_i32(cpu_windowbase_next, cpu_SR[WINDOW_BASE], arg[0]); } static void translate_rsil(DisasContext *dc, const uint32_t arg[], @@ -2972,7 +2979,8 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_entry, .test_ill = test_ill_entry, .test_overflow = test_overflow_entry, - .op_flags = XTENSA_OP_EXIT_TB_M1, + .op_flags = XTENSA_OP_EXIT_TB_M1 | + XTENSA_OP_SYNC_REGISTER_WINDOW, }, { .name = "esync", .translate = translate_nop, @@ -3554,7 +3562,9 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rotw", .translate = translate_rotw, - .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, + .op_flags = XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_M1 | + XTENSA_OP_SYNC_REGISTER_WINDOW, }, { .name = "rsil", .translate = translate_rsil, @@ -4622,7 +4632,9 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){WINDOW_BASE}, - .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, + .op_flags = XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_M1 | + XTENSA_OP_SYNC_REGISTER_WINDOW, }, { .name = "wsr.windowstart", .translate = translate_wsr, @@ -5108,7 +5120,9 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){WINDOW_BASE}, - .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, + .op_flags = XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_M1 | + XTENSA_OP_SYNC_REGISTER_WINDOW, }, { .name = "xsr.windowstart", .translate = translate_xsr, diff --git a/target/xtensa/win_helper.c b/target/xtensa/win_helper.c index 7d793d4f9c..d7a4e27821 100644 --- a/target/xtensa/win_helper.c +++ b/target/xtensa/win_helper.c @@ -96,9 +96,9 @@ void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta) xtensa_rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); } -void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v) +void HELPER(sync_windowbase)(CPUXtensaState *env) { - xtensa_rotate_window_abs(env, v); + xtensa_rotate_window_abs(env, env->windowbase_next); } void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm) @@ -106,9 +106,8 @@ void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm) int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT; env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm; - xtensa_rotate_window(env, callinc); - env->sregs[WINDOW_START] |= - windowstart_bit(env->sregs[WINDOW_BASE], env); + env->windowbase_next = env->sregs[WINDOW_BASE] + callinc; + env->sregs[WINDOW_START] |= windowstart_bit(env->windowbase_next, env); } void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w) @@ -196,11 +195,6 @@ uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc) return ret_pc; } -void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4) -{ - xtensa_rotate_window(env, imm4); -} - void xtensa_restore_owb(CPUXtensaState *env) { xtensa_rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT); From c949009bc0612cbfc7bc5b80c3e9ea3e24313434 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 11 Feb 2019 12:22:29 -0800 Subject: [PATCH 12/40] target/xtensa: only rotate window in the retw helper Move return address calculation and WINDOW_START adjustment out of the retw helper to simplify logic a bit and avoid using registers directly. Pass a0 as a parameter to the helper. Signed-off-by: Max Filippov --- target/xtensa/helper.h | 2 +- target/xtensa/translate.c | 9 +++++++-- target/xtensa/win_helper.c | 8 ++------ 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index b6529a8925..0b9ec670c8 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -7,7 +7,7 @@ DEF_HELPER_1(sync_windowbase, void, env) DEF_HELPER_4(entry, void, env, i32, i32, i32) DEF_HELPER_2(test_ill_retw, void, env, i32) DEF_HELPER_2(test_underflow_retw, void, env, i32) -DEF_HELPER_2(retw, i32, env, i32) +DEF_HELPER_2(retw, void, env, i32) DEF_HELPER_3(window_check, noreturn, env, i32, i32) DEF_HELPER_1(restore_owb, void, env) DEF_HELPER_2(movsp, void, env, i32) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index cbb8d879a8..e63a5f5e71 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -2227,8 +2227,13 @@ static bool test_ill_retw(DisasContext *dc, const uint32_t arg[], static void translate_retw(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - TCGv_i32 tmp = tcg_const_i32(dc->pc); - gen_helper_retw(tmp, cpu_env, tmp); + TCGv_i32 tmp = tcg_const_i32(1); + tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); + tcg_gen_andc_i32(cpu_SR[WINDOW_START], + cpu_SR[WINDOW_START], tmp); + tcg_gen_movi_i32(tmp, dc->pc); + tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30); + gen_helper_retw(cpu_env, cpu_R[0]); gen_jump(dc, tmp); tcg_temp_free(tmp); } diff --git a/target/xtensa/win_helper.c b/target/xtensa/win_helper.c index d7a4e27821..f6f96a64c3 100644 --- a/target/xtensa/win_helper.c +++ b/target/xtensa/win_helper.c @@ -184,15 +184,11 @@ void HELPER(test_underflow_retw)(CPUXtensaState *env, uint32_t pc) } } -uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc) +void HELPER(retw)(CPUXtensaState *env, uint32_t a0) { - int n = (env->regs[0] >> 30) & 0x3; - uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env); - uint32_t ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff); + int n = (a0 >> 30) & 0x3; xtensa_rotate_window(env, -n); - env->sregs[WINDOW_START] &= ~windowstart_bit(windowbase, env); - return ret_pc; } void xtensa_restore_owb(CPUXtensaState *env) From b0b24bdcd9dca02bd5d09e266892d261713cebe8 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 11 Feb 2019 18:53:19 -0800 Subject: [PATCH 13/40] target/xtensa: reorganize register handling in translators To support circular register dependencies in FLIX bundles opcode inputs and outputs must be separate and adjustable. Circular dependencies can be broken by making temporary copies of opcode inputs and substituting them into the arguments array instead of the original registers. E.g. the circular register dependency in the following bundle: { mov a2, a3 ; mov a3, a2 } can be resolved by making copy a2' = a2 and substituting it as input argument of the second opcode: { mov a2, a3 ; mov a3, a2' } Change opcode translator prototype to accept OpcodeArg array as argument. For each register argument initialize OpcodeArg::{in,out} with TCGv_* of the respective register. Don't explicitly use cpu_R in the opcode translators, use OpcodeArg::{in,out} instead. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 15 +- target/xtensa/helper.c | 15 + target/xtensa/translate.c | 700 +++++++++++++++++++------------------- 3 files changed, 386 insertions(+), 344 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index dca4e4b111..bf021f7695 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -345,14 +345,21 @@ typedef struct XtensaMemory { } location[MAX_NMEMORY]; } XtensaMemory; +typedef struct opcode_arg { + uint32_t imm; + uint32_t raw_imm; + void *in; + void *out; +} OpcodeArg; + typedef struct DisasContext DisasContext; -typedef void (*XtensaOpcodeOp)(DisasContext *dc, const uint32_t arg[], +typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]); typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc, - const uint32_t arg[], + const OpcodeArg arg[], const uint32_t par[]); typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc, - const uint32_t arg[], + const OpcodeArg arg[], const uint32_t par[]); enum { @@ -450,6 +457,7 @@ struct XtensaConfig { XtensaOpcodeOps **opcode_ops; const XtensaOpcodeTranslators **opcode_translators; xtensa_regfile a_regfile; + void ***regfile; uint32_t clock_freq_khz; @@ -578,6 +586,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) void xtensa_translate_init(void); +void **xtensa_get_regfile_by_name(const char *name); void xtensa_breakpoint_handler(CPUState *cs); void xtensa_register_core(XtensaConfigList *node); void xtensa_sim_open_console(Chardev *chr); diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 7008c6390d..f4867a9b56 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -91,11 +91,13 @@ static void init_libisa(XtensaConfig *config) unsigned i, j; unsigned opcodes; unsigned formats; + unsigned regfiles; config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL); assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH); opcodes = xtensa_isa_num_opcodes(config->isa); formats = xtensa_isa_num_formats(config->isa); + regfiles = xtensa_isa_num_regfiles(config->isa); config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes); for (i = 0; i < formats; ++i) { @@ -125,6 +127,19 @@ static void init_libisa(XtensaConfig *config) config->opcode_ops[i] = ops; } config->a_regfile = xtensa_regfile_lookup(config->isa, "AR"); + + config->regfile = g_new(void **, regfiles); + for (i = 0; i < regfiles; ++i) { + const char *name = xtensa_regfile_name(config->isa, i); + + config->regfile[i] = xtensa_get_regfile_by_name(name); +#ifdef DEBUG + if (config->regfile[i] == NULL) { + fprintf(stderr, "regfile '%s' not found for %s\n", + name, config->name); + } +#endif + } } static void xtensa_finalize_config(XtensaConfig *config) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index e63a5f5e71..488e46fe31 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -72,7 +72,6 @@ struct DisasContext { unsigned cpenable; uint32_t op_flags; - uint32_t *raw_arg; xtensa_insnbuf insnbuf; xtensa_insnbuf slotbuf; }; @@ -84,6 +83,8 @@ static TCGv_i32 cpu_SR[256]; static TCGv_i32 cpu_UR[256]; static TCGv_i32 cpu_windowbase_next; +static GHashTable *xtensa_regfile_table; + #include "exec/gen-icount.h" typedef struct XtensaReg { @@ -261,6 +262,18 @@ void xtensa_translate_init(void) "windowbase_next"); } +void **xtensa_get_regfile_by_name(const char *name) +{ + if (xtensa_regfile_table == NULL) { + xtensa_regfile_table = g_hash_table_new(g_str_hash, g_str_equal); + g_hash_table_insert(xtensa_regfile_table, + (void *)"AR", (void *)cpu_R); + g_hash_table_insert(xtensa_regfile_table, + (void *)"FR", (void *)cpu_FR); + } + return (void **)g_hash_table_lookup(xtensa_regfile_table, (void *)name); +} + static inline bool option_enabled(DisasContext *dc, int opt) { return xtensa_option_enabled(dc->config, opt); @@ -844,11 +857,11 @@ static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) return m; } -static void gen_zero_check(DisasContext *dc, const uint32_t arg[]) +static void gen_zero_check(DisasContext *dc, const OpcodeArg arg[]) { TCGLabel *label = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0, label); + tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0, label); gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); gen_set_label(label); } @@ -881,8 +894,7 @@ struct opcode_arg_info { struct slot_prop { XtensaOpcodeOps *ops; - uint32_t arg[MAX_OPCODE_ARGS]; - uint32_t raw_arg[MAX_OPCODE_ARGS]; + OpcodeArg arg[MAX_OPCODE_ARGS]; struct opcode_arg_info in[MAX_OPCODE_ARGS]; struct opcode_arg_info out[MAX_OPCODE_ARGS]; unsigned n_in; @@ -1065,12 +1077,9 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) for (slot = 0; slot < slots; ++slot) { xtensa_opcode opc; int opnd, vopnd, opnds; - uint32_t *raw_arg = slot_prop[slot].raw_arg; - uint32_t *arg = slot_prop[slot].arg; + OpcodeArg *arg = slot_prop[slot].arg; XtensaOpcodeOps *ops; - dc->raw_arg = raw_arg; - xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf); opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf); if (opc == XTENSA_UNDEFINED) { @@ -1083,15 +1092,21 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) opnds = xtensa_opcode_num_operands(isa, opc); for (opnd = vopnd = 0; opnd < opnds; ++opnd) { - if (xtensa_operand_is_register(isa, opc, opnd) && - xtensa_operand_regfile(isa, opc, opnd) == - dc->config->a_regfile) { - uint32_t v; + void **register_file = NULL; - xtensa_operand_get_field(isa, opc, opnd, fmt, slot, - dc->slotbuf, &v); - xtensa_operand_decode(isa, opc, opnd, &v); - windowed_register |= 1u << v; + if (xtensa_operand_is_register(isa, opc, opnd)) { + xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd); + + register_file = dc->config->regfile[rf]; + + if (rf == dc->config->a_regfile) { + uint32_t v; + + xtensa_operand_get_field(isa, opc, opnd, fmt, slot, + dc->slotbuf, &v); + xtensa_operand_decode(isa, opc, opnd, &v); + windowed_register |= 1u << v; + } } if (xtensa_operand_is_visible(isa, opc, opnd)) { uint32_t v; @@ -1099,11 +1114,15 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) xtensa_operand_get_field(isa, opc, opnd, fmt, slot, dc->slotbuf, &v); xtensa_operand_decode(isa, opc, opnd, &v); - raw_arg[vopnd] = v; + arg[vopnd].raw_imm = v; if (xtensa_operand_is_PCrelative(isa, opc, opnd)) { xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc); } - arg[vopnd] = v; + arg[vopnd].imm = v; + if (register_file) { + arg[vopnd].in = register_file[v]; + arg[vopnd].out = register_file[v]; + } ++vopnd; } } @@ -1245,7 +1264,6 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) struct slot_prop *pslot = ordered[slot]; XtensaOpcodeOps *ops = pslot->ops; - dc->raw_arg = pslot->raw_arg; ops->translate(dc, pslot->arg, ops->par); } @@ -1511,91 +1529,91 @@ void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, env->pc = data[0]; } -static void translate_abs(DisasContext *dc, const uint32_t arg[], +static void translate_abs(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 zero = tcg_const_i32(0); TCGv_i32 neg = tcg_temp_new_i32(); - tcg_gen_neg_i32(neg, cpu_R[arg[1]]); - tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[arg[0]], - cpu_R[arg[1]], zero, cpu_R[arg[1]], neg); + tcg_gen_neg_i32(neg, arg[1].in); + tcg_gen_movcond_i32(TCG_COND_GE, arg[0].out, + arg[1].in, zero, arg[1].in, neg); tcg_temp_free(neg); tcg_temp_free(zero); } -static void translate_add(DisasContext *dc, const uint32_t arg[], +static void translate_add(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_add_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_add_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_addi(DisasContext *dc, const uint32_t arg[], +static void translate_addi(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_addi_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + tcg_gen_addi_i32(arg[0].out, arg[1].in, arg[2].imm); } -static void translate_addx(DisasContext *dc, const uint32_t arg[], +static void translate_addx(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]); - tcg_gen_add_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]); + tcg_gen_shli_i32(tmp, arg[1].in, par[0]); + tcg_gen_add_i32(arg[0].out, tmp, arg[2].in); tcg_temp_free(tmp); } -static void translate_all(DisasContext *dc, const uint32_t arg[], +static void translate_all(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { uint32_t shift = par[1]; - TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1]); + TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1].imm); TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_and_i32(tmp, cpu_SR[BR], mask); if (par[0]) { - tcg_gen_addi_i32(tmp, tmp, 1 << arg[1]); + tcg_gen_addi_i32(tmp, tmp, 1 << arg[1].imm); } else { tcg_gen_add_i32(tmp, tmp, mask); } - tcg_gen_shri_i32(tmp, tmp, arg[1] + shift); + tcg_gen_shri_i32(tmp, tmp, arg[1].imm + shift); tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], - tmp, arg[0], 1); + tmp, arg[0].imm, 1); tcg_temp_free(mask); tcg_temp_free(tmp); } -static void translate_and(DisasContext *dc, const uint32_t arg[], +static void translate_and(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_and_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_and_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_ball(DisasContext *dc, const uint32_t arg[], +static void translate_ball(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]); - gen_brcond(dc, par[0], tmp, cpu_R[arg[1]], arg[2]); + tcg_gen_and_i32(tmp, arg[0].in, arg[1].in); + gen_brcond(dc, par[0], tmp, arg[1].in, arg[2].imm); tcg_temp_free(tmp); } -static void translate_bany(DisasContext *dc, const uint32_t arg[], +static void translate_bany(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]); - gen_brcondi(dc, par[0], tmp, 0, arg[2]); + tcg_gen_and_i32(tmp, arg[0].in, arg[1].in); + gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); tcg_temp_free(tmp); } -static void translate_b(DisasContext *dc, const uint32_t arg[], +static void translate_b(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_brcond(dc, par[0], cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + gen_brcond(dc, par[0], arg[0].in, arg[1].in, arg[2].imm); } -static void translate_bb(DisasContext *dc, const uint32_t arg[], +static void translate_bb(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifdef TARGET_WORDS_BIGENDIAN @@ -1604,41 +1622,41 @@ static void translate_bb(DisasContext *dc, const uint32_t arg[], TCGv_i32 bit = tcg_const_i32(0x00000001u); #endif TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_R[arg[1]], 0x1f); + tcg_gen_andi_i32(tmp, arg[1].in, 0x1f); #ifdef TARGET_WORDS_BIGENDIAN tcg_gen_shr_i32(bit, bit, tmp); #else tcg_gen_shl_i32(bit, bit, tmp); #endif - tcg_gen_and_i32(tmp, cpu_R[arg[0]], bit); - gen_brcondi(dc, par[0], tmp, 0, arg[2]); + tcg_gen_and_i32(tmp, arg[0].in, bit); + gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); tcg_temp_free(tmp); tcg_temp_free(bit); } -static void translate_bbi(DisasContext *dc, const uint32_t arg[], +static void translate_bbi(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); #ifdef TARGET_WORDS_BIGENDIAN - tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x80000000u >> arg[1]); + tcg_gen_andi_i32(tmp, arg[0].in, 0x80000000u >> arg[1].imm); #else - tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x00000001u << arg[1]); + tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm); #endif - gen_brcondi(dc, par[0], tmp, 0, arg[2]); + gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); tcg_temp_free(tmp); } -static void translate_bi(DisasContext *dc, const uint32_t arg[], +static void translate_bi(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_brcondi(dc, par[0], cpu_R[arg[0]], arg[1], arg[2]); + gen_brcondi(dc, par[0], arg[0].in, arg[1].imm, arg[2].imm); } -static void translate_bz(DisasContext *dc, const uint32_t arg[], +static void translate_bz(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_brcondi(dc, par[0], cpu_R[arg[0]], 0, arg[1]); + gen_brcondi(dc, par[0], arg[0].in, 0, arg[1].imm); } enum { @@ -1649,7 +1667,7 @@ enum { BOOLEAN_XOR, }; -static void translate_boolean(DisasContext *dc, const uint32_t arg[], +static void translate_boolean(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = { @@ -1663,110 +1681,110 @@ static void translate_boolean(DisasContext *dc, const uint32_t arg[], TCGv_i32 tmp1 = tcg_temp_new_i32(); TCGv_i32 tmp2 = tcg_temp_new_i32(); - tcg_gen_shri_i32(tmp1, cpu_SR[BR], arg[1]); - tcg_gen_shri_i32(tmp2, cpu_SR[BR], arg[2]); + tcg_gen_shri_i32(tmp1, cpu_SR[BR], arg[1].imm); + tcg_gen_shri_i32(tmp2, cpu_SR[BR], arg[2].imm); op[par[0]](tmp1, tmp1, tmp2); - tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, arg[0], 1); + tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, arg[0].imm, 1); tcg_temp_free(tmp1); tcg_temp_free(tmp2); } -static void translate_bp(DisasContext *dc, const uint32_t arg[], +static void translate_bp(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[0]); - gen_brcondi(dc, par[0], tmp, 0, arg[1]); + tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[0].imm); + gen_brcondi(dc, par[0], tmp, 0, arg[1].imm); tcg_temp_free(tmp); } -static void translate_call0(DisasContext *dc, const uint32_t arg[], +static void translate_call0(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); - gen_jumpi(dc, arg[0], 0); + gen_jumpi(dc, arg[0].imm, 0); } -static void translate_callw(DisasContext *dc, const uint32_t arg[], +static void translate_callw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 tmp = tcg_const_i32(arg[0]); - gen_callw_slot(dc, par[0], tmp, adjust_jump_slot(dc, arg[0], 0)); + TCGv_i32 tmp = tcg_const_i32(arg[0].imm); + gen_callw_slot(dc, par[0], tmp, adjust_jump_slot(dc, arg[0].imm, 0)); tcg_temp_free(tmp); } -static void translate_callx0(DisasContext *dc, const uint32_t arg[], +static void translate_callx0(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); + tcg_gen_mov_i32(tmp, arg[0].in); tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); gen_jump(dc, tmp); tcg_temp_free(tmp); } -static void translate_callxw(DisasContext *dc, const uint32_t arg[], +static void translate_callxw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); + tcg_gen_mov_i32(tmp, arg[0].in); gen_callw_slot(dc, par[0], tmp, -1); tcg_temp_free(tmp); } -static void translate_clamps(DisasContext *dc, const uint32_t arg[], +static void translate_clamps(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2]); - TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2]) - 1); + TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2].imm); + TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2].imm) - 1); - tcg_gen_smax_i32(tmp1, tmp1, cpu_R[arg[1]]); - tcg_gen_smin_i32(cpu_R[arg[0]], tmp1, tmp2); + tcg_gen_smax_i32(tmp1, tmp1, arg[1].in); + tcg_gen_smin_i32(arg[0].out, tmp1, tmp2); tcg_temp_free(tmp1); tcg_temp_free(tmp2); } -static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[], +static void translate_clrb_expstate(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { /* TODO: GPIO32 may be a part of coprocessor */ - tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0])); + tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0].imm)); } -static void translate_const16(DisasContext *dc, const uint32_t arg[], +static void translate_const16(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 c = tcg_const_i32(arg[1]); + TCGv_i32 c = tcg_const_i32(arg[1].imm); - tcg_gen_deposit_i32(cpu_R[arg[0]], c, cpu_R[arg[0]], 16, 16); + tcg_gen_deposit_i32(arg[0].out, c, arg[0].in, 16, 16); tcg_temp_free(c); } -static void translate_dcache(DisasContext *dc, const uint32_t arg[], +static void translate_dcache(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 addr = tcg_temp_new_i32(); TCGv_i32 res = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); + tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm); tcg_gen_qemu_ld8u(res, addr, dc->cring); tcg_temp_free(addr); tcg_temp_free(res); } -static void translate_depbits(DisasContext *dc, const uint32_t arg[], +static void translate_depbits(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_deposit_i32(cpu_R[arg[1]], cpu_R[arg[1]], cpu_R[arg[0]], - arg[2], arg[3]); + tcg_gen_deposit_i32(arg[1].out, arg[1].in, arg[0].in, + arg[2].imm, arg[3].imm); } -static bool test_ill_entry(DisasContext *dc, const uint32_t arg[], +static bool test_ill_entry(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - if (arg[0] > 3 || !dc->cwoe) { + if (arg[0].imm > 3 || !dc->cwoe) { qemu_log_mask(LOG_GUEST_ERROR, "Illegal entry instruction(pc = %08x)\n", dc->pc); return true; @@ -1775,88 +1793,88 @@ static bool test_ill_entry(DisasContext *dc, const uint32_t arg[], } } -static uint32_t test_overflow_entry(DisasContext *dc, const uint32_t arg[], +static uint32_t test_overflow_entry(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { return 1 << (dc->callinc * 4); } -static void translate_entry(DisasContext *dc, const uint32_t arg[], +static void translate_entry(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 pc = tcg_const_i32(dc->pc); - TCGv_i32 s = tcg_const_i32(arg[0]); - TCGv_i32 imm = tcg_const_i32(arg[1]); + TCGv_i32 s = tcg_const_i32(arg[0].imm); + TCGv_i32 imm = tcg_const_i32(arg[1].imm); gen_helper_entry(cpu_env, pc, s, imm); tcg_temp_free(imm); tcg_temp_free(s); tcg_temp_free(pc); } -static void translate_extui(DisasContext *dc, const uint32_t arg[], +static void translate_extui(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - int maskimm = (1 << arg[3]) - 1; + int maskimm = (1 << arg[3].imm) - 1; TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shri_i32(tmp, cpu_R[arg[1]], arg[2]); - tcg_gen_andi_i32(cpu_R[arg[0]], tmp, maskimm); + tcg_gen_shri_i32(tmp, arg[1].in, arg[2].imm); + tcg_gen_andi_i32(arg[0].out, tmp, maskimm); tcg_temp_free(tmp); } -static void translate_icache(DisasContext *dc, const uint32_t arg[], +static void translate_icache(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY TCGv_i32 addr = tcg_temp_new_i32(); tcg_gen_movi_i32(cpu_pc, dc->pc); - tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); + tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm); gen_helper_itlb_hit_test(cpu_env, addr); tcg_temp_free(addr); #endif } -static void translate_itlb(DisasContext *dc, const uint32_t arg[], +static void translate_itlb(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY TCGv_i32 dtlb = tcg_const_i32(par[0]); - gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb); + gen_helper_itlb(cpu_env, arg[0].in, dtlb); tcg_temp_free(dtlb); #endif } -static void translate_j(DisasContext *dc, const uint32_t arg[], +static void translate_j(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_jumpi(dc, arg[0], 0); + gen_jumpi(dc, arg[0].imm, 0); } -static void translate_jx(DisasContext *dc, const uint32_t arg[], +static void translate_jx(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_jump(dc, cpu_R[arg[0]]); + gen_jump(dc, arg[0].in); } -static void translate_l32e(DisasContext *dc, const uint32_t arg[], +static void translate_l32e(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); gen_load_store_alignment(dc, 2, addr, false); - tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL); + tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->ring, MO_TEUL); tcg_temp_free(addr); } -static void translate_ldst(DisasContext *dc, const uint32_t arg[], +static void translate_ldst(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); if (par[0] & MO_SIZE) { gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]); } @@ -1864,9 +1882,9 @@ static void translate_ldst(DisasContext *dc, const uint32_t arg[], if (par[1]) { tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL); } - tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); + tcg_gen_qemu_st_tl(arg[0].in, addr, dc->cring, par[0]); } else { - tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); + tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->cring, par[0]); if (par[1]) { tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL); } @@ -1874,33 +1892,33 @@ static void translate_ldst(DisasContext *dc, const uint32_t arg[], tcg_temp_free(addr); } -static void translate_l32r(DisasContext *dc, const uint32_t arg[], +static void translate_l32r(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp; if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) { - tmp = tcg_const_i32(dc->raw_arg[1] - 1); + tmp = tcg_const_i32(arg[1].raw_imm - 1); tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp); } else { - tmp = tcg_const_i32(arg[1]); + tmp = tcg_const_i32(arg[1].imm); } - tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring); + tcg_gen_qemu_ld32u(arg[0].out, tmp, dc->cring); tcg_temp_free(tmp); } -static void translate_loop(DisasContext *dc, const uint32_t arg[], +static void translate_loop(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - uint32_t lend = arg[1]; + uint32_t lend = arg[1].imm; - tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1); + tcg_gen_subi_i32(cpu_SR[LCOUNT], arg[0].in, 1); tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next); tcg_gen_movi_i32(cpu_SR[LEND], lend); if (par[0] != TCG_COND_NEVER) { TCGLabel *label = gen_new_label(); - tcg_gen_brcondi_i32(par[0], cpu_R[arg[0]], 0, label); + tcg_gen_brcondi_i32(par[0], arg[0].in, 0, label); gen_jumpi(dc, lend, 1); gen_set_label(label); } @@ -1936,7 +1954,7 @@ enum { MAC16_DX = 0x2, }; -static void translate_mac16(DisasContext *dc, const uint32_t arg[], +static void translate_mac16(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { int op = par[0]; @@ -1949,18 +1967,18 @@ static void translate_mac16(DisasContext *dc, const uint32_t arg[], TCGv_i32 mem32 = tcg_temp_new_i32(); if (ld_offset) { - tcg_gen_addi_i32(vaddr, cpu_R[arg[1]], ld_offset); + tcg_gen_addi_i32(vaddr, arg[1].in, ld_offset); gen_load_store_alignment(dc, 2, vaddr, false); tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); } if (op != MAC16_NONE) { TCGv_i32 m1 = gen_mac16_m(is_m1_sr ? - cpu_SR[MR + arg[off]] : - cpu_R[arg[off]], + cpu_SR[MR + arg[off].imm] : + arg[off].in, half & MAC16_HX, op == MAC16_UMUL); TCGv_i32 m2 = gen_mac16_m(is_m2_sr ? - cpu_SR[MR + arg[off + 1]] : - cpu_R[arg[off + 1]], + cpu_SR[MR + arg[off + 1].imm] : + arg[off + 1].in, half & MAC16_XH, op == MAC16_UMUL); if (op == MAC16_MUL || op == MAC16_UMUL) { @@ -1994,221 +2012,221 @@ static void translate_mac16(DisasContext *dc, const uint32_t arg[], tcg_temp_free(m2); } if (ld_offset) { - tcg_gen_mov_i32(cpu_R[arg[1]], vaddr); - tcg_gen_mov_i32(cpu_SR[MR + arg[0]], mem32); + tcg_gen_mov_i32(arg[1].out, vaddr); + tcg_gen_mov_i32(cpu_SR[MR + arg[0].imm], mem32); } tcg_temp_free(vaddr); tcg_temp_free(mem32); } -static void translate_memw(DisasContext *dc, const uint32_t arg[], +static void translate_memw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); } -static void translate_smin(DisasContext *dc, const uint32_t arg[], +static void translate_smin(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_smin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_smin_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_umin(DisasContext *dc, const uint32_t arg[], +static void translate_umin(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_umin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_umin_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_smax(DisasContext *dc, const uint32_t arg[], +static void translate_smax(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_smax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_smax_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_umax(DisasContext *dc, const uint32_t arg[], +static void translate_umax(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_umax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_umax_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_mov(DisasContext *dc, const uint32_t arg[], +static void translate_mov(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_mov_i32(arg[0].out, arg[1].in); } -static void translate_movcond(DisasContext *dc, const uint32_t arg[], +static void translate_movcond(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 zero = tcg_const_i32(0); - tcg_gen_movcond_i32(par[0], cpu_R[arg[0]], - cpu_R[arg[2]], zero, cpu_R[arg[1]], cpu_R[arg[0]]); + tcg_gen_movcond_i32(par[0], arg[0].out, + arg[2].in, zero, arg[1].in, arg[0].in); tcg_temp_free(zero); } -static void translate_movi(DisasContext *dc, const uint32_t arg[], +static void translate_movi(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_movi_i32(cpu_R[arg[0]], arg[1]); + tcg_gen_movi_i32(arg[0].out, arg[1].imm); } -static void translate_movp(DisasContext *dc, const uint32_t arg[], +static void translate_movp(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 zero = tcg_const_i32(0); TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); + tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2].imm); tcg_gen_movcond_i32(par[0], - cpu_R[arg[0]], tmp, zero, - cpu_R[arg[1]], cpu_R[arg[0]]); + arg[0].out, tmp, zero, + arg[1].in, arg[0].in); tcg_temp_free(tmp); tcg_temp_free(zero); } -static void translate_movsp(DisasContext *dc, const uint32_t arg[], +static void translate_movsp(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_mov_i32(arg[0].out, arg[1].in); } -static void translate_mul16(DisasContext *dc, const uint32_t arg[], +static void translate_mul16(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 v1 = tcg_temp_new_i32(); TCGv_i32 v2 = tcg_temp_new_i32(); if (par[0]) { - tcg_gen_ext16s_i32(v1, cpu_R[arg[1]]); - tcg_gen_ext16s_i32(v2, cpu_R[arg[2]]); + tcg_gen_ext16s_i32(v1, arg[1].in); + tcg_gen_ext16s_i32(v2, arg[2].in); } else { - tcg_gen_ext16u_i32(v1, cpu_R[arg[1]]); - tcg_gen_ext16u_i32(v2, cpu_R[arg[2]]); + tcg_gen_ext16u_i32(v1, arg[1].in); + tcg_gen_ext16u_i32(v2, arg[2].in); } - tcg_gen_mul_i32(cpu_R[arg[0]], v1, v2); + tcg_gen_mul_i32(arg[0].out, v1, v2); tcg_temp_free(v2); tcg_temp_free(v1); } -static void translate_mull(DisasContext *dc, const uint32_t arg[], +static void translate_mull(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mul_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_mul_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_mulh(DisasContext *dc, const uint32_t arg[], +static void translate_mulh(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 lo = tcg_temp_new(); if (par[0]) { - tcg_gen_muls2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_muls2_i32(lo, arg[0].out, arg[1].in, arg[2].in); } else { - tcg_gen_mulu2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_mulu2_i32(lo, arg[0].out, arg[1].in, arg[2].in); } tcg_temp_free(lo); } -static void translate_neg(DisasContext *dc, const uint32_t arg[], +static void translate_neg(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_neg_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_neg_i32(arg[0].out, arg[1].in); } -static void translate_nop(DisasContext *dc, const uint32_t arg[], +static void translate_nop(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { } -static void translate_nsa(DisasContext *dc, const uint32_t arg[], +static void translate_nsa(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_clrsb_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_clrsb_i32(arg[0].out, arg[1].in); } -static void translate_nsau(DisasContext *dc, const uint32_t arg[], +static void translate_nsau(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_clzi_i32(cpu_R[arg[0]], cpu_R[arg[1]], 32); + tcg_gen_clzi_i32(arg[0].out, arg[1].in, 32); } -static void translate_or(DisasContext *dc, const uint32_t arg[], +static void translate_or(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_or_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_or_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_ptlb(DisasContext *dc, const uint32_t arg[], +static void translate_ptlb(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY TCGv_i32 dtlb = tcg_const_i32(par[0]); tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_helper_ptlb(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); + gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb); tcg_temp_free(dtlb); #endif } -static void translate_quos(DisasContext *dc, const uint32_t arg[], +static void translate_quos(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGLabel *label1 = gen_new_label(); TCGLabel *label2 = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[1]], 0x80000000, + tcg_gen_brcondi_i32(TCG_COND_NE, arg[1].in, 0x80000000, label1); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0xffffffff, + tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0xffffffff, label1); - tcg_gen_movi_i32(cpu_R[arg[0]], + tcg_gen_movi_i32(arg[0].out, par[0] ? 0x80000000 : 0); tcg_gen_br(label2); gen_set_label(label1); if (par[0]) { - tcg_gen_div_i32(cpu_R[arg[0]], - cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_div_i32(arg[0].out, + arg[1].in, arg[2].in); } else { - tcg_gen_rem_i32(cpu_R[arg[0]], - cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_rem_i32(arg[0].out, + arg[1].in, arg[2].in); } gen_set_label(label2); } -static void translate_quou(DisasContext *dc, const uint32_t arg[], +static void translate_quou(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_divu_i32(cpu_R[arg[0]], - cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_divu_i32(arg[0].out, + arg[1].in, arg[2].in); } -static void translate_read_impwire(DisasContext *dc, const uint32_t arg[], +static void translate_read_impwire(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { /* TODO: GPIO32 may be a part of coprocessor */ - tcg_gen_movi_i32(cpu_R[arg[0]], 0); + tcg_gen_movi_i32(arg[0].out, 0); } -static void translate_remu(DisasContext *dc, const uint32_t arg[], +static void translate_remu(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_remu_i32(cpu_R[arg[0]], - cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_remu_i32(arg[0].out, + arg[1].in, arg[2].in); } -static void translate_rer(DisasContext *dc, const uint32_t arg[], +static void translate_rer(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_rer(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]]); + gen_helper_rer(arg[0].out, cpu_env, arg[1].in); } -static void translate_ret(DisasContext *dc, const uint32_t arg[], +static void translate_ret(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { gen_jump(dc, cpu_R[0]); } -static bool test_ill_retw(DisasContext *dc, const uint32_t arg[], +static bool test_ill_retw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (!dc->cwoe) { @@ -2224,7 +2242,7 @@ static bool test_ill_retw(DisasContext *dc, const uint32_t arg[], } } -static void translate_retw(DisasContext *dc, const uint32_t arg[], +static void translate_retw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_const_i32(1); @@ -2238,27 +2256,27 @@ static void translate_retw(DisasContext *dc, const uint32_t arg[], tcg_temp_free(tmp); } -static void translate_rfde(DisasContext *dc, const uint32_t arg[], +static void translate_rfde(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]); } -static void translate_rfe(DisasContext *dc, const uint32_t arg[], +static void translate_rfe(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); gen_jump(dc, cpu_SR[EPC1]); } -static void translate_rfi(DisasContext *dc, const uint32_t arg[], +static void translate_rfi(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]); - gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]); + tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0].imm - 2]); + gen_jump(dc, cpu_SR[EPC1 + arg[0].imm - 1]); } -static void translate_rfw(DisasContext *dc, const uint32_t arg[], +static void translate_rfw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_const_i32(1); @@ -2279,33 +2297,33 @@ static void translate_rfw(DisasContext *dc, const uint32_t arg[], gen_jump(dc, cpu_SR[EPC1]); } -static void translate_rotw(DisasContext *dc, const uint32_t arg[], +static void translate_rotw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_addi_i32(cpu_windowbase_next, cpu_SR[WINDOW_BASE], arg[0]); + tcg_gen_addi_i32(cpu_windowbase_next, cpu_SR[WINDOW_BASE], arg[0].imm); } -static void translate_rsil(DisasContext *dc, const uint32_t arg[], +static void translate_rsil(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]); + tcg_gen_mov_i32(arg[0].out, cpu_SR[PS]); tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); - tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]); + tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1].imm); } -static bool test_ill_rsr(DisasContext *dc, const uint32_t arg[], +static bool test_ill_rsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { return !check_sr(dc, par[0], SR_R); } -static void translate_rsr(DisasContext *dc, const uint32_t arg[], +static void translate_rsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_rsr(dc, cpu_R[arg[0]], par[0]); + gen_rsr(dc, arg[0].out, par[0]); } -static void translate_rtlb(DisasContext *dc, const uint32_t arg[], +static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY @@ -2316,26 +2334,26 @@ static void translate_rtlb(DisasContext *dc, const uint32_t arg[], }; TCGv_i32 dtlb = tcg_const_i32(par[0]); - helper[par[1]](cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); + helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb); tcg_temp_free(dtlb); #endif } -static void translate_rur(DisasContext *dc, const uint32_t arg[], +static void translate_rur(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (uregnames[par[0]].name) { - tcg_gen_mov_i32(cpu_R[arg[0]], cpu_UR[par[0]]); + tcg_gen_mov_i32(arg[0].out, cpu_UR[par[0]]); } else { qemu_log_mask(LOG_UNIMP, "RUR %d not implemented\n", par[0]); } } -static void translate_setb_expstate(DisasContext *dc, const uint32_t arg[], +static void translate_setb_expstate(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { /* TODO: GPIO32 may be a part of coprocessor */ - tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0]); + tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0].imm); } #ifdef CONFIG_USER_ONLY @@ -2352,59 +2370,59 @@ static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) } #endif -static void translate_s32c1i(DisasContext *dc, const uint32_t arg[], +static void translate_s32c1i(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_local_new_i32(); TCGv_i32 addr = tcg_temp_local_new_i32(); - tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); - tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + tcg_gen_mov_i32(tmp, arg[0].in); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); gen_load_store_alignment(dc, 2, addr, true); gen_check_atomctl(dc, addr); - tcg_gen_atomic_cmpxchg_i32(cpu_R[arg[0]], addr, cpu_SR[SCOMPARE1], + tcg_gen_atomic_cmpxchg_i32(arg[0].out, addr, cpu_SR[SCOMPARE1], tmp, dc->cring, MO_TEUL); tcg_temp_free(addr); tcg_temp_free(tmp); } -static void translate_s32e(DisasContext *dc, const uint32_t arg[], +static void translate_s32e(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); gen_load_store_alignment(dc, 2, addr, false); - tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL); + tcg_gen_qemu_st_tl(arg[0].in, addr, dc->ring, MO_TEUL); tcg_temp_free(addr); } -static void translate_salt(DisasContext *dc, const uint32_t arg[], +static void translate_salt(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { tcg_gen_setcond_i32(par[0], - cpu_R[arg[0]], - cpu_R[arg[1]], cpu_R[arg[2]]); + arg[0].out, + arg[1].in, arg[2].in); } -static void translate_sext(DisasContext *dc, const uint32_t arg[], +static void translate_sext(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - int shift = 31 - arg[2]; + int shift = 31 - arg[2].imm; if (shift == 24) { - tcg_gen_ext8s_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_ext8s_i32(arg[0].out, arg[1].in); } else if (shift == 16) { - tcg_gen_ext16s_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_ext16s_i32(arg[0].out, arg[1].in); } else { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[arg[1]], shift); - tcg_gen_sari_i32(cpu_R[arg[0]], tmp, shift); + tcg_gen_shli_i32(tmp, arg[1].in, shift); + tcg_gen_sari_i32(arg[0].out, tmp, shift); tcg_temp_free(tmp); } } -static bool test_ill_simcall(DisasContext *dc, const uint32_t arg[], +static bool test_ill_simcall(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifdef CONFIG_USER_ONLY @@ -2418,7 +2436,7 @@ static bool test_ill_simcall(DisasContext *dc, const uint32_t arg[], return ill; } -static void translate_simcall(DisasContext *dc, const uint32_t arg[], +static void translate_simcall(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY @@ -2434,73 +2452,73 @@ static void translate_simcall(DisasContext *dc, const uint32_t arg[], TCGv_i64 tmp = tcg_temp_new_i64(); \ tcg_gen_extu_i32_i64(tmp, reg); \ tcg_gen_##cmd##_i64(v, v, tmp); \ - tcg_gen_extrl_i64_i32(cpu_R[arg[0]], v); \ + tcg_gen_extrl_i64_i32(arg[0].out, v); \ tcg_temp_free_i64(v); \ tcg_temp_free_i64(tmp); \ } while (0) #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) -static void translate_sll(DisasContext *dc, const uint32_t arg[], +static void translate_sll(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (dc->sar_m32_5bit) { - tcg_gen_shl_i32(cpu_R[arg[0]], cpu_R[arg[1]], dc->sar_m32); + tcg_gen_shl_i32(arg[0].out, arg[1].in, dc->sar_m32); } else { TCGv_i64 v = tcg_temp_new_i64(); TCGv_i32 s = tcg_const_i32(32); tcg_gen_sub_i32(s, s, cpu_SR[SAR]); tcg_gen_andi_i32(s, s, 0x3f); - tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]); + tcg_gen_extu_i32_i64(v, arg[1].in); gen_shift_reg(shl, s); tcg_temp_free(s); } } -static void translate_slli(DisasContext *dc, const uint32_t arg[], +static void translate_slli(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - if (arg[2] == 32) { + if (arg[2].imm == 32) { qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n", - arg[0], arg[1]); + arg[0].imm, arg[1].imm); } - tcg_gen_shli_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2] & 0x1f); + tcg_gen_shli_i32(arg[0].out, arg[1].in, arg[2].imm & 0x1f); } -static void translate_sra(DisasContext *dc, const uint32_t arg[], +static void translate_sra(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (dc->sar_m32_5bit) { - tcg_gen_sar_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]); + tcg_gen_sar_i32(arg[0].out, arg[1].in, cpu_SR[SAR]); } else { TCGv_i64 v = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(v, cpu_R[arg[1]]); + tcg_gen_ext_i32_i64(v, arg[1].in); gen_shift(sar); } } -static void translate_srai(DisasContext *dc, const uint32_t arg[], +static void translate_srai(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_sari_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + tcg_gen_sari_i32(arg[0].out, arg[1].in, arg[2].imm); } -static void translate_src(DisasContext *dc, const uint32_t arg[], +static void translate_src(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i64 v = tcg_temp_new_i64(); - tcg_gen_concat_i32_i64(v, cpu_R[arg[2]], cpu_R[arg[1]]); + tcg_gen_concat_i32_i64(v, arg[2].in, arg[1].in); gen_shift(shr); } -static void translate_srl(DisasContext *dc, const uint32_t arg[], +static void translate_srl(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (dc->sar_m32_5bit) { - tcg_gen_shr_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]); + tcg_gen_shr_i32(arg[0].out, arg[1].in, cpu_SR[SAR]); } else { TCGv_i64 v = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]); + tcg_gen_extu_i32_i64(v, arg[1].in); gen_shift(shr); } } @@ -2508,138 +2526,138 @@ static void translate_srl(DisasContext *dc, const uint32_t arg[], #undef gen_shift #undef gen_shift_reg -static void translate_srli(DisasContext *dc, const uint32_t arg[], +static void translate_srli(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_shri_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + tcg_gen_shri_i32(arg[0].out, arg[1].in, arg[2].imm); } -static void translate_ssa8b(DisasContext *dc, const uint32_t arg[], +static void translate_ssa8b(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3); + tcg_gen_shli_i32(tmp, arg[0].in, 3); gen_left_shift_sar(dc, tmp); tcg_temp_free(tmp); } -static void translate_ssa8l(DisasContext *dc, const uint32_t arg[], +static void translate_ssa8l(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3); + tcg_gen_shli_i32(tmp, arg[0].in, 3); gen_right_shift_sar(dc, tmp); tcg_temp_free(tmp); } -static void translate_ssai(DisasContext *dc, const uint32_t arg[], +static void translate_ssai(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 tmp = tcg_const_i32(arg[0]); + TCGv_i32 tmp = tcg_const_i32(arg[0].imm); gen_right_shift_sar(dc, tmp); tcg_temp_free(tmp); } -static void translate_ssl(DisasContext *dc, const uint32_t arg[], +static void translate_ssl(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_left_shift_sar(dc, cpu_R[arg[0]]); + gen_left_shift_sar(dc, arg[0].in); } -static void translate_ssr(DisasContext *dc, const uint32_t arg[], +static void translate_ssr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_right_shift_sar(dc, cpu_R[arg[0]]); + gen_right_shift_sar(dc, arg[0].in); } -static void translate_sub(DisasContext *dc, const uint32_t arg[], +static void translate_sub(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_sub_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_sub_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_subx(DisasContext *dc, const uint32_t arg[], +static void translate_subx(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]); - tcg_gen_sub_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]); + tcg_gen_shli_i32(tmp, arg[1].in, par[0]); + tcg_gen_sub_i32(arg[0].out, tmp, arg[2].in); tcg_temp_free(tmp); } -static void translate_waiti(DisasContext *dc, const uint32_t arg[], +static void translate_waiti(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - gen_waiti(dc, arg[0]); + gen_waiti(dc, arg[0].imm); #endif } -static void translate_wtlb(DisasContext *dc, const uint32_t arg[], +static void translate_wtlb(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY TCGv_i32 dtlb = tcg_const_i32(par[0]); - gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb); + gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb); tcg_temp_free(dtlb); #endif } -static void translate_wer(DisasContext *dc, const uint32_t arg[], +static void translate_wer(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_wer(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]]); + gen_helper_wer(cpu_env, arg[0].in, arg[1].in); } -static void translate_wrmsk_expstate(DisasContext *dc, const uint32_t arg[], +static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { /* TODO: GPIO32 may be a part of coprocessor */ - tcg_gen_and_i32(cpu_UR[EXPSTATE], cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_and_i32(cpu_UR[EXPSTATE], arg[0].in, arg[1].in); } -static bool test_ill_wsr(DisasContext *dc, const uint32_t arg[], +static bool test_ill_wsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { return !check_sr(dc, par[0], SR_W); } -static void translate_wsr(DisasContext *dc, const uint32_t arg[], +static void translate_wsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_wsr(dc, par[0], cpu_R[arg[0]]); + gen_wsr(dc, par[0], arg[0].in); } -static void translate_wur(DisasContext *dc, const uint32_t arg[], +static void translate_wur(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (uregnames[par[0]].name) { - gen_wur(par[0], cpu_R[arg[0]]); + gen_wur(par[0], arg[0].in); } else { qemu_log_mask(LOG_UNIMP, "WUR %d not implemented\n", par[0]); } } -static void translate_xor(DisasContext *dc, const uint32_t arg[], +static void translate_xor(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_xor_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_xor_i32(arg[0].out, arg[1].in, arg[2].in); } -static bool test_ill_xsr(DisasContext *dc, const uint32_t arg[], +static bool test_ill_xsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { return !check_sr(dc, par[0], SR_X); } -static void translate_xsr(DisasContext *dc, const uint32_t arg[], +static void translate_xsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); - gen_rsr(dc, cpu_R[arg[0]], par[0]); + tcg_gen_mov_i32(tmp, arg[0].in); + gen_rsr(dc, arg[0].out, par[0]); gen_wsr(dc, par[0], tmp); tcg_temp_free(tmp); } @@ -5143,17 +5161,17 @@ const XtensaOpcodeTranslators xtensa_core_opcodes = { }; -static void translate_abs_s(DisasContext *dc, const uint32_t arg[], +static void translate_abs_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); + gen_helper_abs_s(arg[0].out, arg[1].in); } -static void translate_add_s(DisasContext *dc, const uint32_t arg[], +static void translate_add_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_add_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[1]], cpu_FR[arg[2]]); + gen_helper_add_s(arg[0].out, cpu_env, + arg[1].in, arg[2].in); } enum { @@ -5166,7 +5184,7 @@ enum { COMPARE_ULE, }; -static void translate_compare_s(DisasContext *dc, const uint32_t arg[], +static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { static void (* const helper[])(TCGv_env env, TCGv_i32 bit, @@ -5179,153 +5197,153 @@ static void translate_compare_s(DisasContext *dc, const uint32_t arg[], [COMPARE_OLE] = gen_helper_ole_s, [COMPARE_ULE] = gen_helper_ule_s, }; - TCGv_i32 bit = tcg_const_i32(1 << arg[0]); + TCGv_i32 bit = tcg_const_i32(1 << arg[0].imm); - helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]); + helper[par[0]](cpu_env, bit, arg[1].in, arg[2].in); tcg_temp_free(bit); } -static void translate_float_s(DisasContext *dc, const uint32_t arg[], +static void translate_float_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 scale = tcg_const_i32(-arg[2]); + TCGv_i32 scale = tcg_const_i32(-arg[2].imm); if (par[0]) { - gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); + gen_helper_uitof(arg[0].out, cpu_env, arg[1].in, scale); } else { - gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); + gen_helper_itof(arg[0].out, cpu_env, arg[1].in, scale); } tcg_temp_free(scale); } -static void translate_ftoi_s(DisasContext *dc, const uint32_t arg[], +static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 rounding_mode = tcg_const_i32(par[0]); - TCGv_i32 scale = tcg_const_i32(arg[2]); + TCGv_i32 scale = tcg_const_i32(arg[2].imm); if (par[1]) { - gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]], + gen_helper_ftoui(arg[0].out, arg[1].in, rounding_mode, scale); } else { - gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]], + gen_helper_ftoi(arg[0].out, arg[1].in, rounding_mode, scale); } tcg_temp_free(rounding_mode); tcg_temp_free(scale); } -static void translate_ldsti(DisasContext *dc, const uint32_t arg[], +static void translate_ldsti(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); gen_load_store_alignment(dc, 2, addr, false); if (par[0]) { - tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); + tcg_gen_qemu_st32(arg[0].in, addr, dc->cring); } else { - tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); + tcg_gen_qemu_ld32u(arg[0].out, addr, dc->cring); } if (par[1]) { - tcg_gen_mov_i32(cpu_R[arg[1]], addr); + tcg_gen_mov_i32(arg[1].out, addr); } tcg_temp_free(addr); } -static void translate_ldstx(DisasContext *dc, const uint32_t arg[], +static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_add_i32(addr, arg[1].in, arg[2].in); gen_load_store_alignment(dc, 2, addr, false); if (par[0]) { - tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); + tcg_gen_qemu_st32(arg[0].in, addr, dc->cring); } else { - tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); + tcg_gen_qemu_ld32u(arg[0].out, addr, dc->cring); } if (par[1]) { - tcg_gen_mov_i32(cpu_R[arg[1]], addr); + tcg_gen_mov_i32(arg[1].out, addr); } tcg_temp_free(addr); } -static void translate_madd_s(DisasContext *dc, const uint32_t arg[], +static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_madd_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); + gen_helper_madd_s(arg[0].out, cpu_env, + arg[0].in, arg[1].in, arg[2].in); } -static void translate_mov_s(DisasContext *dc, const uint32_t arg[], +static void translate_mov_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]); + tcg_gen_mov_i32(arg[0].out, arg[1].in); } -static void translate_movcond_s(DisasContext *dc, const uint32_t arg[], +static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 zero = tcg_const_i32(0); - tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]], - cpu_R[arg[2]], zero, - cpu_FR[arg[1]], cpu_FR[arg[0]]); + tcg_gen_movcond_i32(par[0], arg[0].out, + arg[2].in, zero, + arg[1].in, arg[0].in); tcg_temp_free(zero); } -static void translate_movp_s(DisasContext *dc, const uint32_t arg[], +static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 zero = tcg_const_i32(0); TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); + tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2].imm); tcg_gen_movcond_i32(par[0], - cpu_FR[arg[0]], tmp, zero, - cpu_FR[arg[1]], cpu_FR[arg[0]]); + arg[0].out, tmp, zero, + arg[1].in, arg[0].in); tcg_temp_free(tmp); tcg_temp_free(zero); } -static void translate_mul_s(DisasContext *dc, const uint32_t arg[], +static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_mul_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[1]], cpu_FR[arg[2]]); + gen_helper_mul_s(arg[0].out, cpu_env, + arg[1].in, arg[2].in); } -static void translate_msub_s(DisasContext *dc, const uint32_t arg[], +static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_msub_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); + gen_helper_msub_s(arg[0].out, cpu_env, + arg[0].in, arg[1].in, arg[2].in); } -static void translate_neg_s(DisasContext *dc, const uint32_t arg[], +static void translate_neg_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); + gen_helper_neg_s(arg[0].out, arg[1].in); } -static void translate_rfr_s(DisasContext *dc, const uint32_t arg[], +static void translate_rfr_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]); + tcg_gen_mov_i32(arg[0].out, arg[1].in); } -static void translate_sub_s(DisasContext *dc, const uint32_t arg[], +static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_sub_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[1]], cpu_FR[arg[2]]); + gen_helper_sub_s(arg[0].out, cpu_env, + arg[1].in, arg[2].in); } -static void translate_wfr_s(DisasContext *dc, const uint32_t arg[], +static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]); + tcg_gen_mov_i32(arg[0].out, arg[1].in); } static const XtensaOpcodeOps fpu2000_ops[] = { From 7aa783418707d5a1b1a38fa54b8d4f634e4843de Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 11 Feb 2019 19:16:14 -0800 Subject: [PATCH 14/40] target/xtensa: reorganize access to MAC16 registers libisa represents MAC16 registers m0..m3 as an MR register file. Add this register file and reference its registers directly from the translate_mac16. Drop translator parameter that indicates whether opcode argument is in ar or in mr. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 186 +++++++++++++++++++------------------- 1 file changed, 92 insertions(+), 94 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 488e46fe31..99a0b24d3a 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -79,6 +79,7 @@ struct DisasContext { static TCGv_i32 cpu_pc; static TCGv_i32 cpu_R[16]; static TCGv_i32 cpu_FR[16]; +static TCGv_i32 cpu_MR[4]; static TCGv_i32 cpu_SR[256]; static TCGv_i32 cpu_UR[256]; static TCGv_i32 cpu_windowbase_next; @@ -223,6 +224,9 @@ void xtensa_translate_init(void) "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", }; + static const char * const mregnames[] = { + "m0", "m1", "m2", "m3", + }; int i; cpu_pc = tcg_global_mem_new_i32(cpu_env, @@ -230,14 +234,22 @@ void xtensa_translate_init(void) for (i = 0; i < 16; i++) { cpu_R[i] = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUXtensaState, regs[i]), - regnames[i]); + offsetof(CPUXtensaState, regs[i]), + regnames[i]); } for (i = 0; i < 16; i++) { cpu_FR[i] = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]), - fregnames[i]); + offsetof(CPUXtensaState, + fregs[i].f32[FP_F32_LOW]), + fregnames[i]); + } + + for (i = 0; i < 4; i++) { + cpu_MR[i] = tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, + sregs[MR + i]), + mregnames[i]); } for (i = 0; i < 256; ++i) { @@ -268,6 +280,8 @@ void **xtensa_get_regfile_by_name(const char *name) xtensa_regfile_table = g_hash_table_new(g_str_hash, g_str_equal); g_hash_table_insert(xtensa_regfile_table, (void *)"AR", (void *)cpu_R); + g_hash_table_insert(xtensa_regfile_table, + (void *)"MR", (void *)cpu_MR); g_hash_table_insert(xtensa_regfile_table, (void *)"FR", (void *)cpu_FR); } @@ -1944,24 +1958,12 @@ enum { MAC16_XH = 0x2, }; -enum { - MAC16_AA, - MAC16_AD, - MAC16_DA, - MAC16_DD, - - MAC16_XD = 0x1, - MAC16_DX = 0x2, -}; - static void translate_mac16(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { int op = par[0]; - bool is_m1_sr = par[1] & MAC16_DX; - bool is_m2_sr = par[1] & MAC16_XD; - unsigned half = par[2]; - uint32_t ld_offset = par[3]; + unsigned half = par[1]; + uint32_t ld_offset = par[2]; unsigned off = ld_offset ? 2 : 0; TCGv_i32 vaddr = tcg_temp_new_i32(); TCGv_i32 mem32 = tcg_temp_new_i32(); @@ -1972,13 +1974,9 @@ static void translate_mac16(DisasContext *dc, const OpcodeArg arg[], tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); } if (op != MAC16_NONE) { - TCGv_i32 m1 = gen_mac16_m(is_m1_sr ? - cpu_SR[MR + arg[off].imm] : - arg[off].in, + TCGv_i32 m1 = gen_mac16_m(arg[off].in, half & MAC16_HX, op == MAC16_UMUL); - TCGv_i32 m2 = gen_mac16_m(is_m2_sr ? - cpu_SR[MR + arg[off + 1].imm] : - arg[off + 1].in, + TCGv_i32 m2 = gen_mac16_m(arg[off + 1].in, half & MAC16_XH, op == MAC16_UMUL); if (op == MAC16_MUL || op == MAC16_UMUL) { @@ -3101,11 +3099,11 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_NONE, 0, 0, -4}, + .par = (const uint32_t[]){MAC16_NONE, 0, -4}, }, { .name = "ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_NONE, 0, 0, 4}, + .par = (const uint32_t[]){MAC16_NONE, 0, 4}, }, { .name = "ldpte", .op_flags = XTENSA_OP_ILL, @@ -3188,67 +3186,67 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "mul.aa.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0}, }, { .name = "mul.aa.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0}, }, { .name = "mul.aa.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0}, }, { .name = "mul.aa.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0}, }, { .name = "mul.ad.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0}, }, { .name = "mul.ad.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0}, }, { .name = "mul.ad.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0}, }, { .name = "mul.ad.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0}, }, { .name = "mul.da.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0}, }, { .name = "mul.da.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0}, }, { .name = "mul.da.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0}, }, { .name = "mul.da.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0}, }, { .name = "mul.dd.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0}, }, { .name = "mul.dd.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0}, }, { .name = "mul.dd.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0}, }, { .name = "mul.dd.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0}, }, { .name = "mul16s", .translate = translate_mul16, @@ -3260,198 +3258,198 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "mula.aa.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0}, }, { .name = "mula.aa.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0}, }, { .name = "mula.aa.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0}, }, { .name = "mula.aa.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0}, }, { .name = "mula.ad.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0}, }, { .name = "mula.ad.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0}, }, { .name = "mula.ad.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0}, }, { .name = "mula.ad.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0}, }, { .name = "mula.da.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0}, }, { .name = "mula.da.hh.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, -4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4}, }, { .name = "mula.da.hh.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4}, }, { .name = "mula.da.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0}, }, { .name = "mula.da.hl.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, -4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4}, }, { .name = "mula.da.hl.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4}, }, { .name = "mula.da.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0}, }, { .name = "mula.da.lh.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, -4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4}, }, { .name = "mula.da.lh.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4}, }, { .name = "mula.da.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0}, }, { .name = "mula.da.ll.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, -4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4}, }, { .name = "mula.da.ll.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4}, }, { .name = "mula.dd.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0}, }, { .name = "mula.dd.hh.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, -4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4}, }, { .name = "mula.dd.hh.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4}, }, { .name = "mula.dd.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0}, }, { .name = "mula.dd.hl.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, -4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4}, }, { .name = "mula.dd.hl.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4}, }, { .name = "mula.dd.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0}, }, { .name = "mula.dd.lh.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, -4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4}, }, { .name = "mula.dd.lh.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4}, }, { .name = "mula.dd.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0}, }, { .name = "mula.dd.ll.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, -4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4}, }, { .name = "mula.dd.ll.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 4}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4}, }, { .name = "mull", .translate = translate_mull, }, { .name = "muls.aa.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0}, }, { .name = "muls.aa.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0}, }, { .name = "muls.aa.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0}, }, { .name = "muls.aa.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0}, }, { .name = "muls.ad.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0}, }, { .name = "muls.ad.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0}, }, { .name = "muls.ad.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0}, }, { .name = "muls.ad.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0}, }, { .name = "muls.da.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0}, }, { .name = "muls.da.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0}, }, { .name = "muls.da.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0}, }, { .name = "muls.da.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0}, }, { .name = "muls.dd.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0}, }, { .name = "muls.dd.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0}, }, { .name = "muls.dd.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0}, }, { .name = "muls.dd.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0}, }, { .name = "mulsh", .translate = translate_mulh, @@ -4161,19 +4159,19 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "umul.aa.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_HH, 0}, }, { .name = "umul.aa.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_HL, 0}, }, { .name = "umul.aa.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_LH, 0}, }, { .name = "umul.aa.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_LL, 0}, }, { .name = "waiti", .translate = translate_waiti, From 575e962a01ca502c7c2a8d671f83c5173446c68d Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Thu, 14 Feb 2019 13:27:50 -0800 Subject: [PATCH 15/40] target/xtensa: reorganize access to boolean registers libisa represents boolean registers b0..b16 as a BR register file and as BR4 and BR8 register groups. Add these register files and use OpcodeArg::{in,out} parameters to access boolean registers in translators. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 50 ++++++++++++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 8 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 99a0b24d3a..ca3fce9a7b 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -80,6 +80,9 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_R[16]; static TCGv_i32 cpu_FR[16]; static TCGv_i32 cpu_MR[4]; +static TCGv_i32 cpu_BR[16]; +static TCGv_i32 cpu_BR4[4]; +static TCGv_i32 cpu_BR8[2]; static TCGv_i32 cpu_SR[256]; static TCGv_i32 cpu_UR[256]; static TCGv_i32 cpu_windowbase_next; @@ -227,6 +230,12 @@ void xtensa_translate_init(void) static const char * const mregnames[] = { "m0", "m1", "m2", "m3", }; + static const char * const bregnames[] = { + "b0", "b1", "b2", "b3", + "b4", "b5", "b6", "b7", + "b8", "b9", "b10", "b11", + "b12", "b13", "b14", "b15", + }; int i; cpu_pc = tcg_global_mem_new_i32(cpu_env, @@ -252,6 +261,25 @@ void xtensa_translate_init(void) mregnames[i]); } + for (i = 0; i < 16; i++) { + cpu_BR[i] = tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, + sregs[BR]), + bregnames[i]); + if (i % 4 == 0) { + cpu_BR4[i / 4] = tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, + sregs[BR]), + bregnames[i]); + } + if (i % 8 == 0) { + cpu_BR8[i / 8] = tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, + sregs[BR]), + bregnames[i]); + } + } + for (i = 0; i < 256; ++i) { if (sregnames[i].name) { cpu_SR[i] = tcg_global_mem_new_i32(cpu_env, @@ -284,6 +312,12 @@ void **xtensa_get_regfile_by_name(const char *name) (void *)"MR", (void *)cpu_MR); g_hash_table_insert(xtensa_regfile_table, (void *)"FR", (void *)cpu_FR); + g_hash_table_insert(xtensa_regfile_table, + (void *)"BR", (void *)cpu_BR); + g_hash_table_insert(xtensa_regfile_table, + (void *)"BR4", (void *)cpu_BR4); + g_hash_table_insert(xtensa_regfile_table, + (void *)"BR8", (void *)cpu_BR8); } return (void **)g_hash_table_lookup(xtensa_regfile_table, (void *)name); } @@ -1584,14 +1618,14 @@ static void translate_all(DisasContext *dc, const OpcodeArg arg[], TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1].imm); TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_and_i32(tmp, cpu_SR[BR], mask); + tcg_gen_and_i32(tmp, arg[1].in, mask); if (par[0]) { tcg_gen_addi_i32(tmp, tmp, 1 << arg[1].imm); } else { tcg_gen_add_i32(tmp, tmp, mask); } tcg_gen_shri_i32(tmp, tmp, arg[1].imm + shift); - tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], + tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp, arg[0].imm, 1); tcg_temp_free(mask); tcg_temp_free(tmp); @@ -1695,10 +1729,10 @@ static void translate_boolean(DisasContext *dc, const OpcodeArg arg[], TCGv_i32 tmp1 = tcg_temp_new_i32(); TCGv_i32 tmp2 = tcg_temp_new_i32(); - tcg_gen_shri_i32(tmp1, cpu_SR[BR], arg[1].imm); - tcg_gen_shri_i32(tmp2, cpu_SR[BR], arg[2].imm); + tcg_gen_shri_i32(tmp1, arg[1].in, arg[1].imm); + tcg_gen_shri_i32(tmp2, arg[2].in, arg[2].imm); op[par[0]](tmp1, tmp1, tmp2); - tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, arg[0].imm, 1); + tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp1, arg[0].imm, 1); tcg_temp_free(tmp1); tcg_temp_free(tmp2); } @@ -1708,7 +1742,7 @@ static void translate_bp(DisasContext *dc, const OpcodeArg arg[], { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[0].imm); + tcg_gen_andi_i32(tmp, arg[0].in, 1 << arg[0].imm); gen_brcondi(dc, par[0], tmp, 0, arg[1].imm); tcg_temp_free(tmp); } @@ -2075,7 +2109,7 @@ static void translate_movp(DisasContext *dc, const OpcodeArg arg[], TCGv_i32 zero = tcg_const_i32(0); TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2].imm); + tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); tcg_gen_movcond_i32(par[0], arg[0].out, tmp, zero, arg[1].in, arg[0].in); @@ -5297,7 +5331,7 @@ static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[], TCGv_i32 zero = tcg_const_i32(0); TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2].imm); + tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); tcg_gen_movcond_i32(par[0], arg[0].out, tmp, zero, arg[1].in, arg[0].in); From 89bec9e9117d454d2101f7848475b11677ca99ff Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Tue, 12 Feb 2019 19:10:24 -0800 Subject: [PATCH 16/40] target/xtensa: break circular register dependencies Currently topologic opcode sorting stops at the first detected dependency loop. Introduce struct opcode_arg_copy that describes temporary register copy. Scan remaining opcodes searching for dependencies that can be broken, break them by introducing temporary register copies and record them in an array. In case of success create local temporaries and initialize them with current register values. Share single temporary copy between all register users. Delete temporaries after translation. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 127 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 123 insertions(+), 4 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index ca3fce9a7b..5502b5c0bc 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -935,6 +935,12 @@ static int gen_postprocess(DisasContext *dc, int slot) return slot; } +struct opcode_arg_copy { + uint32_t resource; + void *temp; + OpcodeArg *arg; +}; + struct opcode_arg_info { uint32_t resource; int index; @@ -962,6 +968,11 @@ static uint32_t encode_resource(enum resource_type r, unsigned g, unsigned n) return (r << 24) | (g << 16) | n; } +static enum resource_type get_resource_type(uint32_t resource) +{ + return resource >> 24; +} + /* * a depends on b if b must be executed before a, * because a's side effects will destroy b's inputs. @@ -987,6 +998,49 @@ static bool op_depends_on(const struct slot_prop *a, return false; } +/* + * Try to break a dependency on b, append temporary register copy records + * to the end of copy and update n_copy in case of success. + * This is not always possible: e.g. control flow must always be the last, + * load/store must be first and state dependencies are not supported yet. + */ +static bool break_dependency(struct slot_prop *a, + struct slot_prop *b, + struct opcode_arg_copy *copy, + unsigned *n_copy) +{ + unsigned i = 0; + unsigned j = 0; + unsigned n = *n_copy; + bool rv = false; + + if (a->op_flags & XTENSA_OP_CONTROL_FLOW) { + return false; + } + while (i < a->n_out && j < b->n_in) { + if (a->out[i].resource < b->in[j].resource) { + ++i; + } else if (a->out[i].resource > b->in[j].resource) { + ++j; + } else { + int index = b->in[j].index; + + if (get_resource_type(a->out[i].resource) != RES_REGFILE || + index < 0) { + return false; + } + copy[n].resource = b->in[j].resource; + copy[n].arg = b->arg + index; + ++n; + ++i; + ++j; + rv = true; + } + } + *n_copy = n; + return rv; +} + /* * Calculate evaluation order for slot opcodes. * Build opcode order graph and output its nodes in topological sort order. @@ -995,7 +1049,9 @@ static bool op_depends_on(const struct slot_prop *a, */ static bool tsort(struct slot_prop *slot, struct slot_prop *sorted[], - unsigned n) + unsigned n, + struct opcode_arg_copy *copy, + unsigned *n_copy) { struct tsnode { unsigned n_in_edge; @@ -1008,7 +1064,8 @@ static bool tsort(struct slot_prop *slot, unsigned n_in = 0; unsigned n_out = 0; unsigned n_edge = 0; - unsigned in_idx; + unsigned in_idx = 0; + unsigned node_idx = 0; for (i = 0; i < n; ++i) { node[i].n_in_edge = 0; @@ -1036,7 +1093,8 @@ static bool tsort(struct slot_prop *slot, } } - for (in_idx = 0; in_idx < n_in; ++in_idx) { +again: + for (; in_idx < n_in; ++in_idx) { i = in[in_idx]; sorted[n_out] = slot + i; ++n_out; @@ -1048,6 +1106,29 @@ static bool tsort(struct slot_prop *slot, } } } + if (n_edge) { + for (; node_idx < n; ++node_idx) { + struct tsnode *cnode = node + node_idx; + + if (cnode->n_in_edge) { + for (j = 0; j < cnode->n_out_edge; ++j) { + unsigned k = cnode->out_edge[j]; + + if (break_dependency(slot + k, slot + node_idx, + copy, n_copy) && + --node[k].n_in_edge == 0) { + in[n_in] = k; + ++n_in; + --n_edge; + cnode->out_edge[j] = + cnode->out_edge[cnode->n_out_edge - 1]; + --cnode->n_out_edge; + goto again; + } + } + } + } + } return n_edge == 0; } @@ -1085,6 +1166,15 @@ static int resource_compare(const void *a, const void *b) -1 : (pa->resource > pb->resource ? 1 : 0); } +static int arg_copy_compare(const void *a, const void *b) +{ + const struct opcode_arg_copy *pa = a; + const struct opcode_arg_copy *pb = b; + + return pa->resource < pb->resource ? + -1 : (pa->resource > pb->resource ? 1 : 0); +} + static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) { xtensa_isa isa = dc->config->isa; @@ -1096,6 +1186,8 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) uint32_t op_flags = 0; struct slot_prop slot_prop[MAX_INSN_SLOTS]; struct slot_prop *ordered[MAX_INSN_SLOTS]; + struct opcode_arg_copy arg_copy[MAX_INSN_SLOTS * MAX_OPCODE_ARGS]; + unsigned n_arg_copy = 0; uint32_t debug_cause = 0; uint32_t windowed_register = 0; uint32_t coprocessor = 0; @@ -1250,7 +1342,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } if (slots > 1) { - if (!tsort(slot_prop, ordered, slots)) { + if (!tsort(slot_prop, ordered, slots, arg_copy, &n_arg_copy)) { qemu_log_mask(LOG_UNIMP, "Circular resource dependencies (pc = %08x)\n", dc->pc); @@ -1298,6 +1390,29 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) return; } + if (n_arg_copy) { + uint32_t resource; + void *temp; + unsigned j; + + qsort(arg_copy, n_arg_copy, sizeof(*arg_copy), arg_copy_compare); + for (i = j = 0; i < n_arg_copy; ++i) { + if (i == 0 || arg_copy[i].resource != resource) { + resource = arg_copy[i].resource; + temp = tcg_temp_local_new(); + tcg_gen_mov_i32(temp, arg_copy[i].arg->in); + arg_copy[i].temp = temp; + + if (i != j) { + arg_copy[j] = arg_copy[i]; + } + ++j; + } + arg_copy[i].arg->in = temp; + } + n_arg_copy = j; + } + if (op_flags & XTENSA_OP_DIVIDE_BY_ZERO) { for (slot = 0; slot < slots; ++slot) { if (slot_prop[slot].ops->op_flags & XTENSA_OP_DIVIDE_BY_ZERO) { @@ -1315,6 +1430,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) ops->translate(dc, pslot->arg, ops->par); } + for (i = 0; i < n_arg_copy; ++i) { + tcg_temp_free(arg_copy[i].temp); + } + if (dc->base.is_jmp == DISAS_NEXT) { gen_postprocess(dc, 0); dc->op_flags = 0; From 068e538a54552289a58689f21c99ed3696e59961 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Wed, 13 Feb 2019 17:36:30 -0800 Subject: [PATCH 17/40] target/xtensa: prioritize load/store in FLIX bundles Load/store opcodes may raise MMU exceptions. Normally exceptions should be checked in priority order before any actual operations, but since MMU exceptions are tightly coupled with actual memory access, there's currently no way to do it. Approximate this behavior by executing all load, then all store, and then all other opcodes in the FLIX bundles. Use opcode dependency mechanism to express ordering. Mark load/store opcodes with XTENSA_OP_{LOAD,STORE} flags. Newer libisa has classifier functions that can tell whether opcode is a load or store, but this information is not available in the existing overlays. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 4 ++++ target/xtensa/translate.c | 37 ++++++++++++++++++++++++++++++++----- 2 files changed, 36 insertions(+), 5 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index bf021f7695..a01a94e2a6 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -390,6 +390,10 @@ enum { XTENSA_OP_NAME_ARRAY = 0x8000, XTENSA_OP_CONTROL_FLOW = 0x10000, + XTENSA_OP_STORE = 0x20000, + XTENSA_OP_LOAD = 0x40000, + XTENSA_OP_LOAD_STORE = + XTENSA_OP_LOAD | XTENSA_OP_STORE, }; typedef struct XtensaOpcodeOps { diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 5502b5c0bc..338e6ca70f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -986,6 +986,10 @@ static bool op_depends_on(const struct slot_prop *a, if (a->op_flags & XTENSA_OP_CONTROL_FLOW) { return true; } + if ((a->op_flags & XTENSA_OP_LOAD_STORE) < + (b->op_flags & XTENSA_OP_LOAD_STORE)) { + return true; + } while (i < a->n_out && j < b->n_in) { if (a->out[i].resource < b->in[j].resource) { ++i; @@ -1017,6 +1021,10 @@ static bool break_dependency(struct slot_prop *a, if (a->op_flags & XTENSA_OP_CONTROL_FLOW) { return false; } + if ((a->op_flags & XTENSA_OP_LOAD_STORE) < + (b->op_flags & XTENSA_OP_LOAD_STORE)) { + return false; + } while (i < a->n_out && j < b->n_in) { if (a->out[i].resource < b->in[j].resource) { ++i; @@ -1293,7 +1301,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) if (slots > 1) { slot_prop[slot].n_in = 0; slot_prop[slot].n_out = 0; - slot_prop[slot].op_flags = 0; + slot_prop[slot].op_flags = ops->op_flags & XTENSA_OP_LOAD_STORE; opnds = xtensa_opcode_num_operands(isa, opc); @@ -3223,40 +3231,47 @@ static const XtensaOpcodeOps core_ops[] = { .name = "l16si", .translate = translate_ldst, .par = (const uint32_t[]){MO_TESW, false, false}, + .op_flags = XTENSA_OP_LOAD, }, { .name = "l16ui", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUW, false, false}, + .op_flags = XTENSA_OP_LOAD, }, { .name = "l32ai", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, true, false}, + .op_flags = XTENSA_OP_LOAD, }, { .name = "l32e", .translate = translate_l32e, - .op_flags = XTENSA_OP_PRIVILEGED, + .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_LOAD, }, { .name = (const char * const[]) { "l32i", "l32i.n", NULL, }, .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, false, false}, - .op_flags = XTENSA_OP_NAME_ARRAY, + .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_LOAD, }, { .name = "l32r", .translate = translate_l32r, + .op_flags = XTENSA_OP_LOAD, }, { .name = "l8ui", .translate = translate_ldst, .par = (const uint32_t[]){MO_UB, false, false}, + .op_flags = XTENSA_OP_LOAD, }, { .name = "lddec", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_NONE, 0, -4}, + .op_flags = XTENSA_OP_LOAD, }, { .name = "ldinc", .translate = translate_mac16, .par = (const uint32_t[]){MAC16_NONE, 0, 4}, + .op_flags = XTENSA_OP_LOAD, }, { .name = "ldpte", .op_flags = XTENSA_OP_ILL, @@ -4214,28 +4229,32 @@ static const XtensaOpcodeOps core_ops[] = { .name = "s16i", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUW, false, true}, + .op_flags = XTENSA_OP_STORE, }, { .name = "s32c1i", .translate = translate_s32c1i, + .op_flags = XTENSA_OP_LOAD | XTENSA_OP_STORE, }, { .name = "s32e", .translate = translate_s32e, - .op_flags = XTENSA_OP_PRIVILEGED, + .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_STORE, }, { .name = (const char * const[]) { "s32i", "s32i.n", "s32nb", NULL, }, .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, false, true}, - .op_flags = XTENSA_OP_NAME_ARRAY, + .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_STORE, }, { .name = "s32ri", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, true, true}, + .op_flags = XTENSA_OP_STORE, }, { .name = "s8i", .translate = translate_ldst, .par = (const uint32_t[]){MO_UB, false, true}, + .op_flags = XTENSA_OP_STORE, }, { .name = "salt", .translate = translate_salt, @@ -5525,21 +5544,25 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "lsi", .translate = translate_ldsti, .par = (const uint32_t[]){false, false}, + .op_flags = XTENSA_OP_LOAD, .coprocessor = 0x1, }, { .name = "lsiu", .translate = translate_ldsti, .par = (const uint32_t[]){false, true}, + .op_flags = XTENSA_OP_LOAD, .coprocessor = 0x1, }, { .name = "lsx", .translate = translate_ldstx, .par = (const uint32_t[]){false, false}, + .op_flags = XTENSA_OP_LOAD, .coprocessor = 0x1, }, { .name = "lsxu", .translate = translate_ldstx, .par = (const uint32_t[]){false, true}, + .op_flags = XTENSA_OP_LOAD, .coprocessor = 0x1, }, { .name = "madd.s", @@ -5619,21 +5642,25 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "ssi", .translate = translate_ldsti, .par = (const uint32_t[]){true, false}, + .op_flags = XTENSA_OP_STORE, .coprocessor = 0x1, }, { .name = "ssiu", .translate = translate_ldsti, .par = (const uint32_t[]){true, true}, + .op_flags = XTENSA_OP_STORE, .coprocessor = 0x1, }, { .name = "ssx", .translate = translate_ldstx, .par = (const uint32_t[]){true, false}, + .op_flags = XTENSA_OP_STORE, .coprocessor = 0x1, }, { .name = "ssxu", .translate = translate_ldstx, .par = (const uint32_t[]){true, true}, + .op_flags = XTENSA_OP_STORE, .coprocessor = 0x1, }, { .name = "sub.s", From eb3f4298c96d79a5a67b904c28f293864cc5ccc3 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 03:11:40 -0800 Subject: [PATCH 18/40] target/xtensa: implement PREFCTL SR Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial implementation for this SR. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 1 + target/xtensa/translate.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index a01a94e2a6..4d8152682f 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -131,6 +131,7 @@ enum { ACCLO = 16, ACCHI = 17, MR = 32, + PREFCTL = 40, WINDOW_BASE = 72, WINDOW_START = 73, PTEVADDR = 83, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 338e6ca70f..77bc04d6b0 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -134,6 +134,7 @@ static const XtensaReg sregnames[256] = { [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16), [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16), [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16), + [PREFCTL] = XTENSA_REG_BITS("PREFCTL", XTENSA_OPTION_ALL), [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER), [WINDOW_START] = XTENSA_REG("WINDOW_START", XTENSA_OPTION_WINDOWED_REGISTER), @@ -4152,6 +4153,11 @@ static const XtensaOpcodeOps core_ops[] = { .test_ill = test_ill_rsr, .par = (const uint32_t[]){MISC + 3}, .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "rsr.prefctl", + .translate = translate_rsr, + .test_ill = test_ill_rsr, + .par = (const uint32_t[]){PREFCTL}, }, { .name = "rsr.prid", .translate = translate_rsr, @@ -4777,6 +4783,11 @@ static const XtensaOpcodeOps core_ops[] = { .test_ill = test_ill_wsr, .par = (const uint32_t[]){MMID}, .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "wsr.prefctl", + .translate = translate_wsr, + .test_ill = test_ill_wsr, + .par = (const uint32_t[]){PREFCTL}, }, { .name = "wsr.prid", .translate = translate_wsr, @@ -5265,6 +5276,11 @@ static const XtensaOpcodeOps core_ops[] = { .test_ill = test_ill_xsr, .par = (const uint32_t[]){MISC + 3}, .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "xsr.prefctl", + .translate = translate_xsr, + .test_ill = test_ill_xsr, + .par = (const uint32_t[]){PREFCTL}, }, { .name = "xsr.prid", .translate = translate_xsr, From 0ed040db363bd61bf70f9a464e98229095788bc4 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 01:42:15 -0800 Subject: [PATCH 19/40] tests/tcg/xtensa: indicate failed tests When test suite with multiple tests fails it's not obvious which test failed. Pring "failed" in every invocation of test_fail. Do printing when DEBUG preprocessor macro is defined. Signed-off-by: Max Filippov --- tests/tcg/xtensa/macros.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tests/tcg/xtensa/macros.inc b/tests/tcg/xtensa/macros.inc index 4ebd30ab86..25c7ee479e 100644 --- a/tests/tcg/xtensa/macros.inc +++ b/tests/tcg/xtensa/macros.inc @@ -49,7 +49,9 @@ main: .endm .macro test name - //print test_\name +#ifdef DEBUG + print test_\name +#endif test_init test_\name: .global test_\name @@ -74,6 +76,9 @@ test_\name: l32i a2, a2, 0 movi a3, 1 s8i a3, a2, 0 +#ifdef DEBUG + print failed +#endif j 99f .endm From 906da882911415b493378ed1f8d7925d1871a02e Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 06:04:51 -0800 Subject: [PATCH 20/40] tests/tcg/xtensa: support configurations w/o vecbase Configurations w/o vecbase may have vectors not grouped together and not in fixed order. They may not always be grouped into single output sections by assigning next offset to dot, as it may sometimes move dot backwards and sometimes they may even belong to different memory region. Don't group vectors into single output section. Instead put each vector into its own section ant put it at its default virtual address. Reserve 4KBytes from the default vectors base and put rest of the code and data starting from there. Mark vectors sections as executable, otherwise their contents is discarded. There may be as little as 16 bytes reserved for some vectors, load handler address into a0 and use ret.n to jump there to make vector code fit into this 16 byte space. Signed-off-by: Max Filippov --- tests/tcg/xtensa/Makefile | 4 ++- tests/tcg/xtensa/linker.ld.S | 67 ++++++++++++++++++++++++++---------- tests/tcg/xtensa/vectors.S | 14 ++++++-- 3 files changed, 63 insertions(+), 22 deletions(-) diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index 2f5691f75b..cd21c20287 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -18,6 +18,8 @@ CC = $(CROSS)gcc AS = $(CROSS)gcc -x assembler-with-cpp LD = $(CROSS)ld +vectors_ASFLAGS = -mtext-section-literals + XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa INCLUDE_DIRS = $(XTENSA_SRC_PATH) $(SRC_PATH)/target/xtensa/core-$(CORE) XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS)) @@ -68,7 +70,7 @@ linker.ld: $(XTENSA_SRC_PATH)/linker.ld.S $(CC) $(XTENSA_INC) $(CFLAGS) -c $< -o $@ %.o: $(XTENSA_SRC_PATH)/%.S - $(CC) $(XTENSA_INC) $(ASFLAGS) -c $< -o $@ + $(CC) $(XTENSA_INC) $($*_ASFLAGS) $(ASFLAGS) -c $< -o $@ %.tst: %.o linker.ld $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile $(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@ diff --git a/tests/tcg/xtensa/linker.ld.S b/tests/tcg/xtensa/linker.ld.S index d0f33157ca..ac89b0054e 100644 --- a/tests/tcg/xtensa/linker.ld.S +++ b/tests/tcg/xtensa/linker.ld.S @@ -1,17 +1,29 @@ #include "core-isa.h" -#if XTENSA_HAVE_BE +#ifndef XCHAL_VECBASE_RESET_VADDR +#define XCHAL_VECBASE_RESET_VADDR XCHAL_WINDOW_VECTORS_VADDR +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#endif + +#define RAM_SIZE 0x08000000 /* 128M */ +#define ROM_SIZE 0x00001000 /* 4k */ +#define VECTORS_RESERVED_SIZE 0x1000 + +#if XCHAL_HAVE_BE OUTPUT_FORMAT("elf32-xtensa-be") #else OUTPUT_FORMAT("elf32-xtensa-le") #endif ENTRY(_start) -__DYNAMIC = 0; - MEMORY { - ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = 0x08000000 /* 128M */ - rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = 0x00001000 /* 4k */ + ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = RAM_SIZE + rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = ROM_SIZE } SECTIONS @@ -22,9 +34,9 @@ SECTIONS *(.init.*) } > rom - .vector : - { #if XCHAL_HAVE_WINDOWED + .vector.window XCHAL_WINDOW_VECTORS_VADDR : + { . = XCHAL_WINDOW_OF4_VECOFS; *(.vector.window_overflow_4) . = XCHAL_WINDOW_UF4_VECOFS; @@ -37,41 +49,58 @@ SECTIONS *(.vector.window_overflow_12) . = XCHAL_WINDOW_UF12_VECOFS; *(.vector.window_underflow_12) + } #endif #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2 - . = XCHAL_INTLEVEL2_VECOFS; + .vector.level2 XCHAL_INTLEVEL2_VECTOR_VADDR : + { *(.vector.level2) + } #endif #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3 - . = XCHAL_INTLEVEL3_VECOFS; + .vector.level3 XCHAL_INTLEVEL3_VECTOR_VADDR : + { *(.vector.level3) + } #endif #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4 - . = XCHAL_INTLEVEL4_VECOFS; + .vector.level4 XCHAL_INTLEVEL4_VECTOR_VADDR : + { *(.vector.level4) + } #endif #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5 - . = XCHAL_INTLEVEL5_VECOFS; + .vector.level5 XCHAL_INTLEVEL5_VECTOR_VADDR : + { *(.vector.level5) + } #endif #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6 - . = XCHAL_INTLEVEL6_VECOFS; + .vector.level6 XCHAL_INTLEVEL6_VECTOR_VADDR : + { *(.vector.level6) + } #endif #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7 - . = XCHAL_INTLEVEL7_VECOFS; + .vector.level7 XCHAL_INTLEVEL7_VECTOR_VADDR : + { *(.vector.level7) + } #endif - - . = XCHAL_KERNEL_VECOFS; + .vector.kernel XCHAL_KERNEL_VECTOR_VADDR : + { *(.vector.kernel) - . = XCHAL_USER_VECOFS; + } + .vector.user XCHAL_USER_VECTOR_VADDR : + { *(.vector.user) - . = XCHAL_DOUBLEEXC_VECOFS; + } + .vector.double XCHAL_DOUBLEEXC_VECTOR_VADDR : + { *(.vector.double) - } > ram + } - .vector.text : + .vector.text XCHAL_VECBASE_RESET_VADDR + VECTORS_RESERVED_SIZE : { *(.vector.window_overflow_4.*) *(.vector.window_underflow_4.*) diff --git a/tests/tcg/xtensa/vectors.S b/tests/tcg/xtensa/vectors.S index 6a9cb3cde4..cd48cfb656 100644 --- a/tests/tcg/xtensa/vectors.S +++ b/tests/tcg/xtensa/vectors.S @@ -2,10 +2,20 @@ .macro vector name -.section .vector.\name +.section .vector.\name, "ax" +.global vector_\name +vector_\name\(): j 1f -.section .vector.\name\().text + .literal_position 1: + wsr a0, excsave1 + movi a0, 1f + ret.n + +.section .vector.\name\().text, "ax" + .literal_position +1: + rsr a0, excsave1 wsr a2, excsave1 movi a2, handler_\name l32i a2, a2, 0 From 306a69dad49e6efb6382371a7f4eaa627ef79fab Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 08:20:35 -0800 Subject: [PATCH 21/40] tests/tcg/xtensa: support configs with LITBASE Configurations with LITBASE register may use absolute literals by default. Pass --no-absolute-literals option to assembler to use PC-relative literals instead. Signed-off-by: Max Filippov --- tests/tcg/xtensa/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index cd21c20287..b369380937 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -18,6 +18,7 @@ CC = $(CROSS)gcc AS = $(CROSS)gcc -x assembler-with-cpp LD = $(CROSS)ld +ASFLAGS = -Wa,--no-absolute-literals vectors_ASFLAGS = -mtext-section-literals XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa From fafd5533430cc5c16f419282ae46874271b0d30c Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 06:16:08 -0800 Subject: [PATCH 22/40] tests/tcg/xtensa: don't use optional opcodes in generic code Don't use 'loop' opcode in generic testsuite completion code, only use core opcodes to make it work with any configuration. Signed-off-by: Max Filippov --- tests/tcg/xtensa/macros.inc | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/tests/tcg/xtensa/macros.inc b/tests/tcg/xtensa/macros.inc index 25c7ee479e..93825dc7b5 100644 --- a/tests/tcg/xtensa/macros.inc +++ b/tests/tcg/xtensa/macros.inc @@ -23,11 +23,14 @@ main: movi a0, result sub a2, a2, a0 movi a3, 0 - loopnez a2, 1f - l8ui a2, a0, 0 - or a3, a3, a2 - addi a0, a0, 1 + beqz a2, 2f 1: + l8ui a1, a0, 0 + or a3, a3, a1 + addi a0, a0, 1 + addi a2, a2, -1 + bnez a2, 1b +2: exit .endm From 64eef9bf95a3d3759f2239f9e2b8425fc97858a7 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 06:18:13 -0800 Subject: [PATCH 23/40] tests/tcg/xtensa: fix endianness issues in test_b Use bbci.l/bbsi.l instead of bbci/bbsi, as they are assembly macros that accept little-endian bit number and produce correct immediate for both little and big endian configurations. Choose value loaded into register for bbc/bbs opcodes based on configuration endianness. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_b.S | 40 +++++++++++++++++++++++++++++++-------- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/tests/tcg/xtensa/test_b.S b/tests/tcg/xtensa/test_b.S index 8e81f956df..713a454c53 100644 --- a/tests/tcg/xtensa/test_b.S +++ b/tests/tcg/xtensa/test_b.S @@ -84,12 +84,24 @@ test_end test bbc movi a2, 0xfffffffd - movi a3, 0xffffff01 +#undef BIT +#if XCHAL_HAVE_BE +#define BIT 0xfffffffe +#else +#define BIT 0xffffff01 +#endif + movi a3, BIT bbc a2, a3, 1f test_fail 1: movi a2, 8 - movi a3, 0xffffff03 +#undef BIT +#if XCHAL_HAVE_BE +#define BIT 0xfffffffc +#else +#define BIT 0xffffff03 +#endif + movi a3, BIT bbc a2, a3, 1f j 2f 1: @@ -99,11 +111,11 @@ test_end test bbci movi a2, 0xfffdffff - bbci a2, 17, 1f + bbci.l a2, 17, 1f test_fail 1: movi a2, 0x00020000 - bbci a2, 17, 1f + bbci.l a2, 17, 1f j 2f 1: test_fail @@ -192,12 +204,24 @@ test_end test bbs movi a2, 8 - movi a3, 0xffffff03 +#undef BIT +#if XCHAL_HAVE_BE +#define BIT 0xfffffffc +#else +#define BIT 0xffffff03 +#endif + movi a3, BIT bbs a2, a3, 1f test_fail 1: movi a2, 0xfffffffd - movi a3, 0xffffff01 +#undef BIT +#if XCHAL_HAVE_BE +#define BIT 0xfffffffe +#else +#define BIT 0xffffff01 +#endif + movi a3, BIT bbs a2, a3, 1f j 2f 1: @@ -207,11 +231,11 @@ test_end test bbsi movi a2, 0x00020000 - bbsi a2, 17, 1f + bbsi.l a2, 17, 1f test_fail 1: movi a2, 0xfffdffff - bbsi a2, 17, 1f + bbsi.l a2, 17, 1f j 2f 1: test_fail From 912f161ff7bbb64c7d5b2eb6f81f830c80a6ef9b Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 06:22:41 -0800 Subject: [PATCH 24/40] tests/tcg/xtensa: enable boolean tests Uncomment test_boolean in the test makefile. Make actual tests code conditional on the presence of boolean option in the config. Signed-off-by: Max Filippov --- tests/tcg/xtensa/Makefile | 2 +- tests/tcg/xtensa/test_boolean.S | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index b369380937..aee0134ef5 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -31,7 +31,7 @@ CRT = crt.o vectors.o TESTCASES += test_b.tst TESTCASES += test_bi.tst -#TESTCASES += test_boolean.tst +TESTCASES += test_boolean.tst TESTCASES += test_break.tst TESTCASES += test_bz.tst TESTCASES += test_cache.tst diff --git a/tests/tcg/xtensa/test_boolean.S b/tests/tcg/xtensa/test_boolean.S index eac40e0973..5a850bfe7e 100644 --- a/tests/tcg/xtensa/test_boolean.S +++ b/tests/tcg/xtensa/test_boolean.S @@ -2,6 +2,8 @@ test_suite boolean +#if XCHAL_HAVE_BOOLEANS + test all4 movi a2, 0xfec0 wsr a2, br @@ -20,4 +22,6 @@ test all4 assert eq, a2, a3 test_end +#endif + test_suite_end From 66c58ba71b2ed49b5908ae4db146986d053e46be Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 06:24:38 -0800 Subject: [PATCH 25/40] tests/tcg/xtensa: conditionalize debug option tests Make debug tests conditional on the presence of the debug option in the config and tests that depend on the presence/number of instruction or data breakpoint registers on the corresponding definitions. Use configured debug interrupt level instead of the hardcoded value to set up IRQ handler and access debug EPC register. Signed-off-by: Max Filippov --- tests/tcg/xtensa/macros.inc | 3 +++ tests/tcg/xtensa/test_break.S | 27 ++++++++++++++++++--------- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/tests/tcg/xtensa/macros.inc b/tests/tcg/xtensa/macros.inc index 93825dc7b5..5265c8606b 100644 --- a/tests/tcg/xtensa/macros.inc +++ b/tests/tcg/xtensa/macros.inc @@ -97,3 +97,6 @@ test_\name: movi a3, \addr s32i a3, a2, 0 .endm + +#define glue(a, b) _glue(a, b) +#define _glue(a, b) a ## b diff --git a/tests/tcg/xtensa/test_break.S b/tests/tcg/xtensa/test_break.S index 775cd7c260..3379a3f9f0 100644 --- a/tests/tcg/xtensa/test_break.S +++ b/tests/tcg/xtensa/test_break.S @@ -1,10 +1,13 @@ #include "macros.inc" -#define debug_level 6 -#define debug_vector level6 - test_suite break +#if XCHAL_HAVE_DEBUG + +#define debug_level XCHAL_DEBUGLEVEL +#define debug_vector glue(level, XCHAL_DEBUGLEVEL) +#define EPC_DEBUG glue(epc, XCHAL_DEBUGLEVEL) + test break set_vector debug_vector, 0 rsil a2, debug_level @@ -21,7 +24,7 @@ test break and a2, a2, a3 movi a3, 0x10 | debug_level assert eq, a2, a3 - rsr a2, epc6 + rsr a2, EPC_DEBUG movi a3, 1b assert eq, a2, a3 rsr a2, debugcause @@ -45,7 +48,7 @@ test breakn and a2, a2, a3 movi a3, 0x10 | debug_level assert eq, a2, a3 - rsr a2, epc6 + rsr a2, EPC_DEBUG movi a3, 1b assert eq, a2, a3 rsr a2, debugcause @@ -53,6 +56,7 @@ test breakn assert eq, a2, a3 test_end +#if XCHAL_NUM_IBREAK test ibreak set_vector debug_vector, 0 rsil a2, debug_level @@ -83,7 +87,7 @@ test ibreak and a2, a2, a3 movi a3, 0x10 | debug_level assert eq, a2, a3 - rsr a2, epc6 + rsr a2, EPC_DEBUG movi a3, 1b assert eq, a2, a3 rsr a2, debugcause @@ -110,7 +114,7 @@ test ibreak_remove and a2, a2, a3 movi a3, 0x10 | debug_level assert eq, a2, a3 - rsr a2, epc6 + rsr a2, EPC_DEBUG movi a3, 2b assert eq, a2, a3 rsr a2, debugcause @@ -141,6 +145,7 @@ test ibreak_priority movi a3, 0x2 assert eq, a2, a3 test_end +#endif test icount set_vector debug_vector, 2f @@ -158,7 +163,7 @@ test icount 2: movi a2, 0 wsr a2, icountlevel - rsr a2, epc6 + rsr a2, EPC_DEBUG movi a3, 1b assert eq, a2, a3 rsr a2, debugcause @@ -167,7 +172,7 @@ test icount test_end .macro check_dbreak dr - rsr a2, epc6 + rsr a2, EPC_DEBUG movi a3, 1b assert eq, a2, a3 rsr a2, debugcause @@ -194,6 +199,7 @@ test_end reset_ps .endm +#if XCHAL_NUM_DBREAK test dbreak_exact dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui @@ -253,5 +259,8 @@ test dbreak_invalid dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i test_end +#endif + +#endif test_suite_end From ecf5b577592be61b78b5d67724a1ebf559c9e695 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 06:32:45 -0800 Subject: [PATCH 26/40] tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_cache.S | 66 +++++++++++++++++++++++++++-------- 1 file changed, 52 insertions(+), 14 deletions(-) diff --git a/tests/tcg/xtensa/test_cache.S b/tests/tcg/xtensa/test_cache.S index 6b2df9734b..7e6ba4c18a 100644 --- a/tests/tcg/xtensa/test_cache.S +++ b/tests/tcg/xtensa/test_cache.S @@ -7,6 +7,8 @@ test_suite cache +#if XCHAL_HAVE_PTP_MMU + .macro pf_op op \op a2, 0 \op a3, 0 @@ -18,14 +20,23 @@ test prefetch movi a3, 0xd8000000 /* non-cacheable */ movi a4, 0x00001235 /* unmapped */ +#if XCHAL_DCACHE_SIZE pf_op dpfr pf_op dpfro pf_op dpfw pf_op dpfwo +#endif +#ifdef XCHAL_ICACHE_SIZE pf_op ipf - +#endif +#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY +#if XCHAL_DCACHE_LINE_LOCKABLE dpfl a2, 0 +#endif +#if XCHAL_ICACHE_LINE_LOCKABLE ipfl a2, 0 +#endif +#endif test_end .macro cache_fault op, addr, exc_code @@ -46,10 +57,16 @@ test_end assert eq, a2, a3 .endm +#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY + +#if XCHAL_DCACHE_LINE_LOCKABLE test dpfl_tlb_miss cache_fault dpfl, 0x00002345, 24 test_end +#endif +#if XCHAL_DCACHE_SIZE +#if XCHAL_DCACHE_IS_WRITEBACK test dhwb_tlb_miss cache_fault dhwb, 0x00002345, 24 test_end @@ -57,16 +74,21 @@ test_end test dhwbi_tlb_miss cache_fault dhwbi, 0x00002345, 24 test_end +#endif test dhi_tlb_miss cache_fault dhi, 0x00002345, 24 test_end +#if XCHAL_DCACHE_LINE_LOCKABLE test dhu_tlb_miss cache_fault dhu, 0x00002345, 24 test_end +#endif +#endif - +#if XCHAL_ICACHE_SIZE +#if XCHAL_ICACHE_LINE_LOCKABLE test ipfl_tlb_miss cache_fault ipfl, 0x00002345, 16 test_end @@ -74,24 +96,40 @@ test_end test ihu_tlb_miss cache_fault ihu, 0x00002345, 16 test_end +#endif test ihi_tlb_miss cache_fault ihi, 0x00002345, 16 test_end +#endif + +#endif + +#endif test_suite_end -.macro cache_all op1, op2, size, linesize - movi a2, 0 - movi a3, \size -1: - \op1 a2, 0 - \op2 a2, 0 - addi a2, a2, \linesize - bltu a2, a3, 1b -.endm - cache_unlock_invalidate: - cache_all diu, dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE - cache_all iiu, iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE +#if XCHAL_DCACHE_SIZE + movi a2, 0 + movi a3, XCHAL_DCACHE_SIZE +1: +#if XCHAL_DCACHE_LINE_LOCKABLE + diu a2, 0 +#endif + dii a2, 0 + addi a2, a2, XCHAL_DCACHE_LINESIZE + bltu a2, a3, 1b +#endif +#if XCHAL_ICACHE_SIZE + movi a2, 0 + movi a3, XCHAL_ICACHE_SIZE +1: +#if XCHAL_ICACHE_LINE_LOCKABLE + iiu a2, 0 +#endif + iii a2, 0 + addi a2, a2, XCHAL_ICACHE_LINESIZE + bltu a2, a3, 1b +#endif ret From 50f0171a9543f7a40abdbd36714fb1201cdc47b0 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 06:40:38 -0800 Subject: [PATCH 27/40] tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_clamps.S | 4 ++++ tests/tcg/xtensa/test_loop.S | 4 ++++ tests/tcg/xtensa/test_mac16.S | 4 ++++ tests/tcg/xtensa/test_max.S | 4 ++++ tests/tcg/xtensa/test_min.S | 4 ++++ tests/tcg/xtensa/test_mul16.S | 4 ++++ tests/tcg/xtensa/test_mul32.S | 4 ++++ tests/tcg/xtensa/test_nsa.S | 4 ++++ tests/tcg/xtensa/test_quo.S | 4 ++++ tests/tcg/xtensa/test_rem.S | 4 ++++ tests/tcg/xtensa/test_rst0.S | 8 ++++++++ tests/tcg/xtensa/test_sext.S | 4 ++++ 12 files changed, 52 insertions(+) diff --git a/tests/tcg/xtensa/test_clamps.S b/tests/tcg/xtensa/test_clamps.S index 3efabfd9d3..d9b2c38ac1 100644 --- a/tests/tcg/xtensa/test_clamps.S +++ b/tests/tcg/xtensa/test_clamps.S @@ -2,6 +2,8 @@ test_suite clamps +#if XCHAL_HAVE_CLAMPS + test clamps movi a2, 0 movi a3, 0 @@ -39,4 +41,6 @@ test clamps assert eq, a3, a2 test_end +#endif + test_suite_end diff --git a/tests/tcg/xtensa/test_loop.S b/tests/tcg/xtensa/test_loop.S index 5755578d01..0cfd8661ea 100644 --- a/tests/tcg/xtensa/test_loop.S +++ b/tests/tcg/xtensa/test_loop.S @@ -2,6 +2,8 @@ test_suite loop +#if XCHAL_HAVE_LOOPS + test loop movi a2, 0 movi a3, 5 @@ -160,4 +162,6 @@ test loopgtz 1: test_end +#endif + test_suite_end diff --git a/tests/tcg/xtensa/test_mac16.S b/tests/tcg/xtensa/test_mac16.S index 512025d842..ee0cedd2ae 100644 --- a/tests/tcg/xtensa/test_mac16.S +++ b/tests/tcg/xtensa/test_mac16.S @@ -2,6 +2,8 @@ test_suite mac16 +#if XCHAL_HAVE_MAC16 + #define ext16(v) (((v) & 0xffff) | (((v) & 0x8000) * 0x1ffffffe)) #define mul16(a, b) ((ext16(a) * ext16(b))) @@ -240,4 +242,6 @@ test mula_dd_lddec .text test_end +#endif + test_suite_end diff --git a/tests/tcg/xtensa/test_max.S b/tests/tcg/xtensa/test_max.S index 3caa207ea5..f349d578e3 100644 --- a/tests/tcg/xtensa/test_max.S +++ b/tests/tcg/xtensa/test_max.S @@ -2,6 +2,8 @@ test_suite max +#if XCHAL_HAVE_MINMAX + test max movi a2, 0xffffffff movi a3, 1 @@ -78,4 +80,6 @@ test maxu assert eq, a3, a4 test_end +#endif + test_suite_end diff --git a/tests/tcg/xtensa/test_min.S b/tests/tcg/xtensa/test_min.S index 551cf591e5..89ee10334f 100644 --- a/tests/tcg/xtensa/test_min.S +++ b/tests/tcg/xtensa/test_min.S @@ -2,6 +2,8 @@ test_suite min +#if XCHAL_HAVE_MINMAX + test min movi a2, 0xffffffff movi a3, 1 @@ -78,4 +80,6 @@ test minu assert eq, a3, a4 test_end +#endif + test_suite_end diff --git a/tests/tcg/xtensa/test_mul16.S b/tests/tcg/xtensa/test_mul16.S index 98fa7042b5..32507f7f1e 100644 --- a/tests/tcg/xtensa/test_mul16.S +++ b/tests/tcg/xtensa/test_mul16.S @@ -2,6 +2,8 @@ test_suite mul16 +#if XCHAL_HAVE_MUL16 + test mul16u_pp movi a2, 0x137f5a5a mov a3, a2 @@ -80,4 +82,6 @@ test mul16s_nn assert eq, a3, a6 test_end +#endif + test_suite_end diff --git a/tests/tcg/xtensa/test_mul32.S b/tests/tcg/xtensa/test_mul32.S index b288ead9f6..862d45abce 100644 --- a/tests/tcg/xtensa/test_mul32.S +++ b/tests/tcg/xtensa/test_mul32.S @@ -2,6 +2,8 @@ test_suite mul32 +#if XCHAL_HAVE_MUL32 + test mull movi a2, 0x137f5a5a mov a3, a2 @@ -15,6 +17,8 @@ test mull assert eq, a3, a6 test_end +#endif + /* unfortunately dc232b doesn't have muluh/mulsh*/ test_suite_end diff --git a/tests/tcg/xtensa/test_nsa.S b/tests/tcg/xtensa/test_nsa.S index 479b2e2429..0af7d1f50d 100644 --- a/tests/tcg/xtensa/test_nsa.S +++ b/tests/tcg/xtensa/test_nsa.S @@ -2,6 +2,8 @@ test_suite nsa +#if XCHAL_HAVE_NSA + test nsa movi a2, 0 movi a3, 31 @@ -56,4 +58,6 @@ test nsau assert eq, a3, a2 test_end +#endif + test_suite_end diff --git a/tests/tcg/xtensa/test_quo.S b/tests/tcg/xtensa/test_quo.S index 5b3ae383d0..32886b913b 100644 --- a/tests/tcg/xtensa/test_quo.S +++ b/tests/tcg/xtensa/test_quo.S @@ -2,6 +2,8 @@ test_suite quo +#if XCHAL_HAVE_DIV32 + test quou_pp movi a2, 0x5a5a137f mov a3, a2 @@ -144,4 +146,6 @@ test quos_exc assert eq, a2, a3 test_end +#endif + test_suite_end diff --git a/tests/tcg/xtensa/test_rem.S b/tests/tcg/xtensa/test_rem.S index 6357e520d9..0b96bb3390 100644 --- a/tests/tcg/xtensa/test_rem.S +++ b/tests/tcg/xtensa/test_rem.S @@ -2,6 +2,8 @@ test_suite rem +#if XCHAL_HAVE_DIV32 + test remu_pp movi a2, 0x5a5a137f mov a3, a2 @@ -144,4 +146,6 @@ test rems_exc assert eq, a2, a3 test_end +#endif + test_suite_end diff --git a/tests/tcg/xtensa/test_rst0.S b/tests/tcg/xtensa/test_rst0.S index a73366b120..143e90b401 100644 --- a/tests/tcg/xtensa/test_rst0.S +++ b/tests/tcg/xtensa/test_rst0.S @@ -54,6 +54,8 @@ test add assert eq, a4, a6 test_end +#if XCHAL_HAVE_ADDX + test addx2 movi a2, 0x137fa5a5 mov a3, a2 @@ -93,6 +95,8 @@ test addx8 assert eq, a4, a6 test_end +#endif + test sub movi a2, 0x137fa5a5 mov a3, a2 @@ -106,6 +110,8 @@ test sub assert eq, a4, a6 test_end +#if XCHAL_HAVE_ADDX + test subx2 movi a2, 0x137fa5a5 mov a3, a2 @@ -145,4 +151,6 @@ test subx8 assert eq, a4, a6 test_end +#endif + test_suite_end diff --git a/tests/tcg/xtensa/test_sext.S b/tests/tcg/xtensa/test_sext.S index 087a6333a4..483d2176e4 100644 --- a/tests/tcg/xtensa/test_sext.S +++ b/tests/tcg/xtensa/test_sext.S @@ -2,6 +2,8 @@ test_suite sext +#if XCHAL_HAVE_SEXT + test sext movi a2, 0xffffff5a movi a3, 0x0000005a @@ -66,4 +68,6 @@ test sext_same_rs assert eq, a3, a2 test_end +#endif + test_suite_end From 9c988226195c3d2b611352a76c0d8bd835ecb75b Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 06:50:10 -0800 Subject: [PATCH 28/40] tests/tcg/xtensa: conditionalize interrupt tests Make interrupt tests conditional on the presence of interrupt option and on the presence of level-1 and high level software interrupts. Don't use hard-coded interrupt level for the high level interrupt tests, choose high level software IRQ and use its configured level. Signed-off-by: Max Filippov --- tests/tcg/xtensa/macros.inc | 3 ++ tests/tcg/xtensa/test_interrupt.S | 88 ++++++++++++++++++++++++------- 2 files changed, 73 insertions(+), 18 deletions(-) diff --git a/tests/tcg/xtensa/macros.inc b/tests/tcg/xtensa/macros.inc index 5265c8606b..36536ed8a4 100644 --- a/tests/tcg/xtensa/macros.inc +++ b/tests/tcg/xtensa/macros.inc @@ -100,3 +100,6 @@ test_\name: #define glue(a, b) _glue(a, b) #define _glue(a, b) a ## b + +#define glue3(a, b, c) _glue3(a, b, c) +#define _glue3(a, b, c) a ## b ## c diff --git a/tests/tcg/xtensa/test_interrupt.S b/tests/tcg/xtensa/test_interrupt.S index 876683518e..efedc43f60 100644 --- a/tests/tcg/xtensa/test_interrupt.S +++ b/tests/tcg/xtensa/test_interrupt.S @@ -1,15 +1,59 @@ #include "macros.inc" -#define LSBIT(v) ((v) ^ ((v) & ((v) - 1))) +#define LSBIT(v) ((v) & -(v)) + +#define LEVEL_MASK(x) glue3(XCHAL_INTLEVEL, x, _MASK) +#define LEVEL_SOFT_MASK(x) (LEVEL_MASK(x) & XCHAL_INTTYPE_MASK_SOFTWARE) + +#define L1_SOFT_MASK LEVEL_SOFT_MASK(1) +#define L1_SOFT LSBIT(L1_SOFT_MASK) + +#if LEVEL_SOFT_MASK(2) +#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(2) +#elif LEVEL_SOFT_MASK(3) +#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(3) +#elif LEVEL_SOFT_MASK(4) +#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(4) +#elif LEVEL_SOFT_MASK(5) +#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(5) +#elif LEVEL_SOFT_MASK(6) +#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(6) +#else +#define HIGH_LEVEL_SOFT_MASK 0 +#endif + +#define HIGH_LEVEL_SOFT LSBIT(HIGH_LEVEL_SOFT_MASK) + +#if LEVEL_SOFT_MASK(2) +#define HIGH_LEVEL_SOFT_LEVEL 2 +#elif LEVEL_SOFT_MASK(3) +#define HIGH_LEVEL_SOFT_LEVEL 3 +#elif LEVEL_SOFT_MASK(4) +#define HIGH_LEVEL_SOFT_LEVEL 4 +#elif LEVEL_SOFT_MASK(5) +#define HIGH_LEVEL_SOFT_LEVEL 5 +#elif LEVEL_SOFT_MASK(6) +#define HIGH_LEVEL_SOFT_LEVEL 6 +#else +#define HIGH_LEVEL_SOFT_LEVEL 0 +#endif test_suite interrupt +#if XCHAL_HAVE_INTERRUPTS + .macro clear_interrupts movi a2, 0 wsr a2, intenable +#if XCHAL_NUM_TIMERS wsr a2, ccompare0 +#endif +#if XCHAL_NUM_TIMERS > 1 wsr a2, ccompare1 +#endif +#if XCHAL_NUM_TIMERS > 2 wsr a2, ccompare2 +#endif esync rsr a2, interrupt wsr a2, intclear @@ -44,11 +88,12 @@ test rsil assert eqi, a2, 0 test_end +#if L1_SOFT test soft_disabled set_vector kernel, 1f clear_interrupts - movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE) + movi a2, L1_SOFT wsr a2, intset esync rsr a3, interrupt @@ -70,7 +115,7 @@ test soft_intenable set_vector kernel, 1f clear_interrupts - movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE) + movi a2, L1_SOFT wsr a2, intset esync rsr a3, interrupt @@ -89,7 +134,7 @@ test soft_rsil set_vector kernel, 1f clear_interrupts - movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE) + movi a2, L1_SOFT wsr a2, intset esync rsr a3, interrupt @@ -108,7 +153,7 @@ test soft_waiti set_vector kernel, 1f clear_interrupts - movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE) + movi a2, L1_SOFT wsr a2, intset esync rsr a3, interrupt @@ -127,7 +172,7 @@ test soft_user set_vector user, 2f clear_interrupts - movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE) + movi a2, L1_SOFT wsr a2, intset esync rsr a3, interrupt @@ -147,12 +192,13 @@ test soft_user check_l1 test_end +#if HIGH_LEVEL_SOFT test soft_priority set_vector kernel, 1f - set_vector level3, 2f + set_vector glue(level, HIGH_LEVEL_SOFT_LEVEL), 2f clear_interrupts - movi a2, XCHAL_INTTYPE_MASK_SOFTWARE + movi a2, L1_SOFT | HIGH_LEVEL_SOFT wsr a2, intenable rsil a3, 0 esync @@ -164,17 +210,20 @@ test soft_priority rsr a2, ps movi a3, 0x1f /* EXCM | INTMASK */ and a2, a2, a3 - movi a3, 0x13 + movi a3, 0x10 | HIGH_LEVEL_SOFT_LEVEL assert eq, a2, a3 /* EXCM and INTMASK are set for high-priority interrupt */ test_end +#endif +#endif +#if HIGH_LEVEL_SOFT test eps_epc_rfi - set_vector level3, 3f + set_vector glue(level, HIGH_LEVEL_SOFT_LEVEL), 3f clear_interrupts reset_ps - movi a2, XCHAL_INTTYPE_MASK_SOFTWARE + movi a2, L1_SOFT_MASK | HIGH_LEVEL_SOFT_MASK wsr a2, intenable rsil a3, 0 rsr a3, ps @@ -185,23 +234,26 @@ test eps_epc_rfi 2: test_fail 3: - rsr a2, eps3 + rsr a2, glue(eps, HIGH_LEVEL_SOFT_LEVEL) assert eq, a2, a3 - rsr a2, epc3 + rsr a2, glue(epc, HIGH_LEVEL_SOFT_LEVEL) movi a3, 1b assert ge, a2, a3 movi a3, 2b assert ge, a3, a2 movi a2, 4f - wsr a2, epc3 - movi a2, 0x40003 - wsr a2, eps3 - rfi 3 + wsr a2, glue(epc, HIGH_LEVEL_SOFT_LEVEL) + movi a2, 0x40000 | HIGH_LEVEL_SOFT_LEVEL + wsr a2, glue(eps, HIGH_LEVEL_SOFT_LEVEL) + rfi HIGH_LEVEL_SOFT_LEVEL test_fail 4: rsr a2, ps - movi a3, 0x40003 + movi a3, 0x40000 | HIGH_LEVEL_SOFT_LEVEL assert eq, a2, a3 test_end +#endif + +#endif test_suite_end From 02a5a4a8774b65ca619297bba4fe6e51bf9023d1 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 06:55:15 -0800 Subject: [PATCH 29/40] tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_timer.S | 48 ++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/tests/tcg/xtensa/test_timer.S b/tests/tcg/xtensa/test_timer.S index 6cda71adbb..1ec8e20883 100644 --- a/tests/tcg/xtensa/test_timer.S +++ b/tests/tcg/xtensa/test_timer.S @@ -2,6 +2,8 @@ #define CCOUNT_SHIFT 4 #define WAIT_LOOPS 20 +#define level1 kernel +#define INTERRUPT_LEVEL(n) glue3(XCHAL_INT, n, _LEVEL) .macro make_ccount_delta target, delta rsr \delta, ccount @@ -13,6 +15,8 @@ test_suite timer +#if XCHAL_HAVE_CCOUNT + test ccount rsr a3, ccount rsr a4, ccount @@ -32,14 +36,20 @@ test ccount_write assert ltu, a3, a4 test_end +#if XCHAL_NUM_TIMERS + test ccount_update_deadline movi a2, 0 wsr a2, intenable rsr a2, interrupt wsr a2, intclear movi a2, 0 +#if XCHAL_NUM_TIMERS > 1 wsr a2, ccompare1 +#endif +#if XCHAL_NUM_TIMERS > 2 wsr a2, ccompare2 +#endif movi a2, 0x12345678 wsr a2, ccompare0 rsr a3, interrupt @@ -59,8 +69,12 @@ test ccompare rsr a2, interrupt wsr a2, intclear movi a2, 0 +#if XCHAL_NUM_TIMERS > 1 wsr a2, ccompare1 +#endif +#if XCHAL_NUM_TIMERS > 2 wsr a2, ccompare2 +#endif make_ccount_delta a2, a15 wsr a2, ccompare0 @@ -76,6 +90,7 @@ test ccompare assert nei, a5, 0 test_end +#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1 test ccompare0_interrupt set_vector kernel, 2f movi a2, 0 @@ -83,8 +98,12 @@ test ccompare0_interrupt rsr a2, interrupt wsr a2, intclear movi a2, 0 +#if XCHAL_NUM_TIMERS > 1 wsr a2, ccompare1 +#endif +#if XCHAL_NUM_TIMERS > 2 wsr a2, ccompare2 +#endif movi a3, WAIT_LOOPS make_ccount_delta a2, a15 @@ -104,16 +123,21 @@ test ccompare0_interrupt rsr a2, exccause assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ test_end +#endif + +#if XCHAL_NUM_TIMERS > 1 test ccompare1_interrupt - set_vector level3, 2f + set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT)), 2f movi a2, 0 wsr a2, intenable rsr a2, interrupt wsr a2, intclear movi a2, 0 wsr a2, ccompare0 +#if XCHAL_NUM_TIMERS > 2 wsr a2, ccompare2 +#endif movi a3, WAIT_LOOPS make_ccount_delta a2, a15 @@ -123,7 +147,7 @@ test ccompare1_interrupt assert eqi, a2, 0 movi a2, 1 << XCHAL_TIMER1_INTERRUPT wsr a2, intenable - rsil a2, 2 + rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) - 1 loop a3, 1f nop 1: @@ -131,8 +155,11 @@ test ccompare1_interrupt 2: test_end +#endif +#if XCHAL_NUM_TIMERS > 2 + test ccompare2_interrupt - set_vector level5, 2f + set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT)), 2f movi a2, 0 wsr a2, intenable rsr a2, interrupt @@ -149,7 +176,7 @@ test ccompare2_interrupt assert eqi, a2, 0 movi a2, 1 << XCHAL_TIMER2_INTERRUPT wsr a2, intenable - rsil a2, 4 + rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) - 1 loop a3, 1f nop 1: @@ -157,6 +184,8 @@ test ccompare2_interrupt 2: test_end +#endif + test ccompare_interrupt_masked set_vector kernel, 2f movi a2, 0 @@ -164,11 +193,15 @@ test ccompare_interrupt_masked rsr a2, interrupt wsr a2, intclear movi a2, 0 +#if XCHAL_NUM_TIMERS > 2 wsr a2, ccompare2 +#endif movi a3, 2 * WAIT_LOOPS make_ccount_delta a2, a15 +#if XCHAL_NUM_TIMERS > 1 wsr a2, ccompare1 +#endif add a2, a2, a15 wsr a2, ccompare0 rsync @@ -194,11 +227,15 @@ test ccompare_interrupt_masked_waiti rsr a2, interrupt wsr a2, intclear movi a2, 0 +#if XCHAL_NUM_TIMERS > 2 wsr a2, ccompare2 +#endif movi a3, 2 * WAIT_LOOPS make_ccount_delta a2, a15 +#if XCHAL_NUM_TIMERS > 1 wsr a2, ccompare1 +#endif add a2, a2, a15 wsr a2, ccompare0 rsync @@ -214,4 +251,7 @@ test ccompare_interrupt_masked_waiti assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ test_end +#endif +#endif + test_suite_end From 50d3a0feaec5a88d5b3c1235fd058ff19f489885 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 06:58:23 -0800 Subject: [PATCH 30/40] tests/tcg/xtensa: conditionalize and expand SR tests Make tests for specific special registers conditional on the presence of the options that add these registers and test that the registers are not accessible otherwise. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_sr.S | 133 +++++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/tests/tcg/xtensa/test_sr.S b/tests/tcg/xtensa/test_sr.S index 052f1e04a7..e64653b877 100644 --- a/tests/tcg/xtensa/test_sr.S +++ b/tests/tcg/xtensa/test_sr.S @@ -42,50 +42,183 @@ test_end test_sr_mask \sr, \conf, 7 .endm +#if XCHAL_HAVE_MAC16 test_sr acchi, 1 test_sr acclo, 1 +#else +test_sr_mask /*acchi*/17, 0, 0 +test_sr_mask /*acclo*/16, 0, 0 +#endif + +#if XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000 +test_sr atomctl, 1 +#else test_sr_mask /*atomctl*/99, 0, 0 +#endif + +#if XCHAL_HAVE_BOOLEANS +test_sr br, 1 +#else test_sr_mask /*br*/4, 0, 0 +#endif + test_sr_mask /*cacheattr*/98, 0, 0 + +#if XCHAL_HAVE_CCOUNT test_sr ccompare0, 1 test_sr ccount, 1 +#else +test_sr_mask /*ccompare0*/240, 0, 0 +test_sr_mask /*ccount*/234, 0, 0 +#endif + +#if XCHAL_HAVE_CP test_sr cpenable, 1 +#else +test_sr_mask /*cpenable*/224, 0, 0 +#endif + +#if XCHAL_HAVE_DEBUG +#if XCHAL_NUM_DBREAK test_sr dbreaka0, 1 test_sr dbreakc0, 1 +#endif test_sr_mask debugcause, 1, 1 +#else +test_sr_mask /*dbreaka0*/144, 0, 0 +test_sr_mask /*dbreakc0*/160, 0, 0 +test_sr_mask /*debugcause*/233, 0, 0 +#endif + test_sr depc, 1 + +#if XCHAL_HAVE_PTP_MMU test_sr dtlbcfg, 1 +#else +test_sr_mask /*dtlbcfg*/92, 0, 0 +#endif + test_sr epc1, 1 + +#if XCHAL_NUM_INTLEVELS > 1 test_sr epc2, 1 test_sr eps2, 1 +#else +test_sr_mask /*epc2*/178, 0, 0 +test_sr_mask /*eps2*/194, 0, 0 +#endif + test_sr exccause, 1 test_sr excsave1, 1 + +#if XCHAL_NUM_INTLEVELS > 1 test_sr excsave2, 1 +#else +test_sr_mask /*excsave2*/210, 0, 0 +#endif + test_sr excvaddr, 1 + +#if XCHAL_HAVE_DEBUG +#if XCHAL_NUM_IBREAK test_sr ibreaka0, 1 test_sr ibreakenable, 1 +#endif test_sr icount, 1 test_sr icountlevel, 1 +#else +test_sr_mask /*ibreaka0*/128, 0, 0 +test_sr_mask /*ibreakenable*/96, 0, 0 +test_sr_mask /*icount*/236, 0, 0 +test_sr_mask /*icountlevel*/237, 0, 0 +#endif + test_sr_mask /*intclear*/227, 0, 2 test_sr_mask /*interrupt*/226, 0, 3 test_sr intenable, 1 + +#if XCHAL_HAVE_PTP_MMU test_sr itlbcfg, 1 +#else +test_sr_mask /*itlbcfg*/91, 0, 0 +#endif + +#if XCHAL_HAVE_LOOPS test_sr lbeg, 1 test_sr lcount, 1 test_sr lend, 1 +#else +test_sr_mask /*lbeg*/0, 0, 0 +test_sr_mask /*lcount*/2, 0, 0 +test_sr_mask /*lend*/1, 0, 0 +#endif + +#if XCHAL_HAVE_ABSOLUTE_LITERALS test_sr litbase, 1 +#else +test_sr_mask /*litbase*/5, 0, 0 +#endif + +#if XCHAL_HAVE_MAC16 test_sr m0, 1 +#else +test_sr_mask /*m0*/32, 0, 0 +#endif + +#if XCHAL_HW_VERSION >= 250000 +test_sr_mask /*memctl*/97, 0, 7 +#else test_sr_mask /*memctl*/97, 0, 0 +#endif + +#if XCHAL_NUM_MISC_REGS test_sr misc0, 1 +#else +test_sr_mask /*misc0*/244, 0, 0 +#endif + +#if XCHAL_HAVE_PREFETCH +test_sr prefctl, 1 +#else test_sr_mask /*prefctl*/40, 0, 0 +#endif + +#if XCHAL_HAVE_PRID test_sr_mask /*prid*/235, 0, 1 +#else +test_sr_mask /*prid*/235, 0, 0 +#endif + test_sr ps, 1 + +#if XCHAL_HAVE_PTP_MMU test_sr ptevaddr, 1 test_sr rasid, 1 +#else +test_sr_mask /*ptevaddr*/83, 0, 0 +test_sr_mask /*rasid*/90, 0, 0 +#endif + test_sr sar, 1 + +#if XCHAL_HAVE_S32C1I test_sr scompare1, 1 +#else +test_sr_mask /*scompare1*/12, 0, 0 +#endif + +#if XCHAL_HAVE_VECBASE test_sr vecbase, 1 +#else +test_sr_mask /*vecbase*/231, 0, 0 +#endif + +#if XCHAL_HAVE_WINDOWED test_sr windowbase, 1 test_sr windowstart, 1 +#else +test_sr_mask /*windowbase*/72, 0, 0 +test_sr_mask /*windowstart*/73, 0, 0 +#endif test_suite_end From 9b2d08a066b85315fa41a3bbe8cc2186278c0f79 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 07:12:37 -0800 Subject: [PATCH 31/40] tests/tcg/xtensa: fix SR tests for big endian configs SR tests generate instructions that the assembler does not recognize and thus must take care about configuration endianness. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_sr.S | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/tests/tcg/xtensa/test_sr.S b/tests/tcg/xtensa/test_sr.S index e64653b877..b1a91a0637 100644 --- a/tests/tcg/xtensa/test_sr.S +++ b/tests/tcg/xtensa/test_sr.S @@ -2,11 +2,23 @@ test_suite sr +#if XCHAL_HAVE_BE +#define LOW__SR 0x04 +#define HI_RSR 0x30 +#define HI_WSR 0x31 +#define HI_XSR 0x16 +#else +#define LOW__SR 0x40 +#define HI_RSR 0x03 +#define HI_WSR 0x13 +#define HI_XSR 0x61 +#endif + .macro sr_op sym, op_sym, op_byte, sr .if \sym \op_sym a4, \sr .else - .byte 0x40, \sr, \op_byte + .byte LOW__SR, \sr, \op_byte .endif .endm @@ -32,9 +44,9 @@ test_suite sr .macro test_sr_mask sr, sym, mask test \sr - test_sr_op \sym, \mask & 1, rsr, 0x03, \sr - test_sr_op \sym, \mask & 2, wsr, 0x13, \sr - test_sr_op \sym, \mask & 4, xsr, 0x61, \sr + test_sr_op \sym, \mask & 1, rsr, HI_RSR, \sr + test_sr_op \sym, \mask & 2, wsr, HI_WSR, \sr + test_sr_op \sym, \mask & 4, xsr, HI_XSR, \sr test_end .endm From 00988da4860c363522daa39709cb5985d6a6033a Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 07:15:10 -0800 Subject: [PATCH 32/40] tests/tcg/xtensa: conditionalize and fix s32c1i tests Make s32c1i tests conditional on the presence of this option. Initialize ATOMCTL SR when it's present to allow RCW transactions on uncached memory. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_s32c1i.S | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tests/tcg/xtensa/test_s32c1i.S b/tests/tcg/xtensa/test_s32c1i.S index 93b575db95..2885d9d003 100644 --- a/tests/tcg/xtensa/test_s32c1i.S +++ b/tests/tcg/xtensa/test_s32c1i.S @@ -2,7 +2,13 @@ test_suite s32c1i +#if XCHAL_HAVE_S32C1I + test s32c1i_nowrite +#if XCHAL_HW_VERSION >= 230000 + movi a2, 0x29 + wsr a2, atomctl +#endif movi a2, 1f movi a3, 1 wsr a3, scompare1 @@ -20,6 +26,10 @@ test s32c1i_nowrite test_end test s32c1i_write +#if XCHAL_HW_VERSION >= 230000 + movi a2, 0x29 + wsr a2, atomctl +#endif movi a2, 1f movi a3, 3 wsr a3, scompare1 @@ -36,4 +46,6 @@ test s32c1i_write .text test_end +#endif + test_suite_end From c20e10eac83c1ec5c5c06f737bd06428fa55cbbc Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 07:16:55 -0800 Subject: [PATCH 33/40] tests/tcg/xtensa: conditionalize windowed register tests Make windowed register tests conditional on the presence of this option. Fix tests to work correctly for both 32 and 64 physical registers. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_windowed.S | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/tests/tcg/xtensa/test_windowed.S b/tests/tcg/xtensa/test_windowed.S index d851e8f43c..5ead90a790 100644 --- a/tests/tcg/xtensa/test_windowed.S +++ b/tests/tcg/xtensa/test_windowed.S @@ -2,10 +2,12 @@ test_suite windowed +#if XCHAL_HAVE_WINDOWED + .altmacro .macro reset_window start - movi a2, 0xff + movi a2, 0xffff wsr a2, windowstart rsync movi a2, 0 @@ -105,7 +107,8 @@ test_end movi a3, 0x4001f assert eq, a2, a3 rsr a2, windowbase - assert eqi, a2, 8 - ((\window) / 4) + movi a3, (XCHAL_NUM_AREGS - (\window)) / 4 + assert eq, a2, a3 rsr a2, windowstart assert eqi, a2, 1 rfwu @@ -116,8 +119,8 @@ test_end rsr a2, windowbase assert eqi, a2, 0 rsr a2, windowstart - assert bsi, a2, 0 - assert bsi, a2, 8 - ((\window) / 4) + assert bsi.l, a2, 0 + assert bsi.l, a2, (XCHAL_NUM_AREGS - (\window)) / 4 .endm test underflow @@ -132,7 +135,7 @@ test_end .macro retw_test window - reset_window %(1 | (1 << (8 - (\window) / 4))) + reset_window %(1 | (1 << ((XCHAL_NUM_AREGS - \window) / 4))) reset_ps ssai 2 @@ -147,10 +150,11 @@ test_end movi a3, 0x4000f assert eq, a2, a3 rsr a2, windowbase - assert eqi, a2, 8 - ((\window) / 4) + movi a3, (XCHAL_NUM_AREGS - (\window)) / 4 + assert eq, a2, a3 rsr a2, windowstart - assert bci, a2, 0 - assert bsi, a2, 8 - ((\window) / 4) + assert bci.l, a2, 0 + assert bsi.l, a2, (XCHAL_NUM_AREGS - (\window)) / 4 .endm test retw @@ -180,7 +184,7 @@ test movsp set_vector kernel, 0 - reset_window 0x81 + reset_window %(0x1 | (1 << ((XCHAL_NUM_AREGS / 4) - 1))) reset_ps movsp a2, a3 @@ -211,8 +215,16 @@ test rotw movi a3, 0x16 movi a7, 0x17 +#if XCHAL_NUM_AREGS == 32 movi a2, 0x44 wsr a2, windowstart +#elif XCHAL_NUM_AREGS == 64 + movi a2, 0x4004 + wsr a2, windowstart + rotw -8 +#else +#error XCHAL_NUM_AREGS unsupported +#endif rsync movi a2, 0x10 @@ -350,4 +362,6 @@ test entry_overflow all_entry_overflow_tests test_end +#endif + test_suite_end From 3db8a95e70be544af5969a54da5fad5ddc3090e1 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 18 Feb 2019 07:19:02 -0800 Subject: [PATCH 34/40] tests/tcg/xtensa: conditionalize MMU-related tests Make MMU-related tests conditional on the presence of MMUv2 option. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_mmu.S | 4 ++++ tests/tcg/xtensa/test_phys_mem.S | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/tests/tcg/xtensa/test_mmu.S b/tests/tcg/xtensa/test_mmu.S index a15316ffb3..4cbd6ef4f9 100644 --- a/tests/tcg/xtensa/test_mmu.S +++ b/tests/tcg/xtensa/test_mmu.S @@ -2,6 +2,8 @@ test_suite mmu +#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY + .purgem test_init .macro clean_tlb_way way, page_size, n_entries @@ -740,4 +742,6 @@ test cross_page_tb assert eq, a2, a3 test_end +#endif + test_suite_end diff --git a/tests/tcg/xtensa/test_phys_mem.S b/tests/tcg/xtensa/test_phys_mem.S index aae0a793a7..9bb3ee3866 100644 --- a/tests/tcg/xtensa/test_phys_mem.S +++ b/tests/tcg/xtensa/test_phys_mem.S @@ -2,6 +2,8 @@ test_suite phys_mem +#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY + .purgem test_init .macro test_init @@ -67,6 +69,8 @@ test write_get_pte_no_phys assert eq, a2, a3 test_end +#endif + test inst_fetch_no_phys set_vector kernel, 2f From ebbd775aab3a15b3d631e6a262353ece4575fcf5 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Wed, 3 Oct 2018 12:43:54 -0700 Subject: [PATCH 35/40] tests/tcg/xtensa: add test for FLIX Signed-off-by: Max Filippov --- tests/tcg/xtensa/Makefile | 1 + tests/tcg/xtensa/test_flix.S | 60 ++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 tests/tcg/xtensa/test_flix.S diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index aee0134ef5..bd94ba6fe5 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -38,6 +38,7 @@ TESTCASES += test_cache.tst TESTCASES += test_clamps.tst TESTCASES += test_extui.tst TESTCASES += test_fail.tst +TESTCASES += test_flix.tst TESTCASES += test_interrupt.tst TESTCASES += test_loop.tst TESTCASES += test_mac16.tst diff --git a/tests/tcg/xtensa/test_flix.S b/tests/tcg/xtensa/test_flix.S new file mode 100644 index 0000000000..7c259e7018 --- /dev/null +++ b/tests/tcg/xtensa/test_flix.S @@ -0,0 +1,60 @@ +#include "macros.inc" + +test_suite flix + +#if XCHAL_HAVE_FLIX3 + +test misc + { + mov a3, a4 + mov a2, a3 + nop + } + { + nop + bne.w18 a2, a3, 1f + } + movi a2, 1f + { + mov a2, a3 + mov a3, a2 + nop + } + { + l32i a2, a3, 0 + add a4, a4, a2 + nop + } + { + mov a3, a4 + jx a3 + nop + } +1: +test_end + +test sum + + movi a2, 0 + movi a3, 2f + movi a4, 0 + movi a5, 4 + + loop a5, 1f + { + l32i a2, a3, 0 + addi a3, a3, 4 + add a4, a4, a2 + } +1: + add a4, a4, a2 + assert eqi, a4, 10 + .data +2: + .word 1, 2, 3, 4 + .previous +test_end + +#endif + +test_suite_end From 5e33b037b5153936c503b17f3e6b40fa34265268 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Thu, 8 Mar 2012 03:00:31 +0400 Subject: [PATCH 36/40] tests/tcg/xtensa: add LSCI/LSCX group tests Signed-off-by: Max Filippov --- tests/tcg/xtensa/Makefile | 1 + tests/tcg/xtensa/test_lsc.S | 122 ++++++++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+) create mode 100644 tests/tcg/xtensa/test_lsc.S diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index bd94ba6fe5..c2bc278be5 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -41,6 +41,7 @@ TESTCASES += test_fail.tst TESTCASES += test_flix.tst TESTCASES += test_interrupt.tst TESTCASES += test_loop.tst +TESTCASES += test_lsc.tst TESTCASES += test_mac16.tst TESTCASES += test_max.tst TESTCASES += test_min.tst diff --git a/tests/tcg/xtensa/test_lsc.S b/tests/tcg/xtensa/test_lsc.S new file mode 100644 index 0000000000..0578bf19e7 --- /dev/null +++ b/tests/tcg/xtensa/test_lsc.S @@ -0,0 +1,122 @@ +#include "macros.inc" + +test_suite lsc + +#if XCHAL_HAVE_FP + +test lsi + movi a2, 1 + wsr a2, cpenable + + movi a2, 1f + lsi f0, a2, 0 + lsi f1, a2, 4 + lsiu f2, a2, 8 + movi a3, 1f + 8 + assert eq, a2, a3 + rfr a2, f0 + movi a3, 0x3f800000 + assert eq, a2, a3 + rfr a2, f1 + movi a3, 0x40000000 + assert eq, a2, a3 + rfr a2, f2 + movi a3, 0x40400000 + assert eq, a2, a3 +.data + .align 4 +1: +.float 1, 2, 3 +.text +test_end + +test ssi + movi a2, 1f + movi a3, 0x40800000 + wfr f3, a3 + ssi f3, a2, 0 + movi a3, 0x40a00000 + wfr f4, a3 + ssi f4, a2, 4 + movi a3, 0x40c00000 + wfr f5, a3 + ssiu f5, a2, 8 + movi a3, 1f + 8 + assert eq, a2, a3 + l32i a4, a2, -8 + movi a3, 0x40800000 + assert eq, a4, a3 + l32i a4, a2, -4 + movi a3, 0x40a00000 + assert eq, a4, a3 + l32i a4, a2, 0 + movi a3, 0x40c00000 + assert eq, a4, a3 +.data + .align 4 +1: +.float 0, 0, 0 +.text +test_end + +test lsx + movi a2, 1f + movi a3, 0 + lsx f6, a2, a3 + movi a3, 4 + lsx f7, a2, a3 + movi a3, 8 + lsxu f8, a2, a3 + movi a3, 1f + 8 + assert eq, a2, a3 + rfr a2, f6 + movi a3, 0x40e00000 + assert eq, a2, a3 + rfr a2, f7 + movi a3, 0x41000000 + assert eq, a2, a3 + rfr a2, f8 + movi a3, 0x41100000 + assert eq, a2, a3 +.data + .align 4 +1: +.float 7, 8, 9 +.text +test_end + +test ssx + movi a2, 1f + movi a3, 0 + movi a4, 0x41200000 + wfr f9, a4 + ssx f9, a2, a3 + movi a3, 4 + movi a4, 0x41300000 + wfr f10, a4 + ssx f10, a2, a3 + movi a3, 8 + movi a4, 0x41400000 + wfr f11, a4 + ssxu f11, a2, a3 + movi a3, 1f + 8 + assert eq, a2, a3 + l32i a4, a2, -8 + movi a3, 0x41200000 + assert eq, a4, a3 + l32i a4, a2, -4 + movi a3, 0x41300000 + assert eq, a4, a3 + l32i a4, a2, 0 + movi a3, 0x41400000 + assert eq, a4, a3 +.data + .align 4 +1: +.float 0, 0, 0 +.text +test_end + +#endif + +test_suite_end From 9d012e8ec2c75cf9d114e272cddbadcabd44f4f8 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Thu, 6 Sep 2012 04:23:44 +0400 Subject: [PATCH 37/40] tests/tcg/xtensa: add FP0 group arithmetic tests Test arithmetic operations for normal, NaN and Inf arguments. Signed-off-by: Max Filippov --- tests/tcg/xtensa/Makefile | 1 + tests/tcg/xtensa/macros.inc | 17 +++ tests/tcg/xtensa/test_fp0_arith.S | 173 ++++++++++++++++++++++++++++++ 3 files changed, 191 insertions(+) create mode 100644 tests/tcg/xtensa/test_fp0_arith.S diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index c2bc278be5..eea269a36e 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -39,6 +39,7 @@ TESTCASES += test_clamps.tst TESTCASES += test_extui.tst TESTCASES += test_fail.tst TESTCASES += test_flix.tst +TESTCASES += test_fp0_arith.tst TESTCASES += test_interrupt.tst TESTCASES += test_loop.tst TESTCASES += test_lsc.tst diff --git a/tests/tcg/xtensa/macros.inc b/tests/tcg/xtensa/macros.inc index 36536ed8a4..aa8f95bce8 100644 --- a/tests/tcg/xtensa/macros.inc +++ b/tests/tcg/xtensa/macros.inc @@ -98,6 +98,23 @@ test_\name: s32i a3, a2, 0 .endm +.macro dump r +#ifdef DEBUG +.data +.align 4 +1: .word 0 +.text + movi a4, 1b + s32i a2, a4, 0 + movi a2, 4 + movi a3, 1 + movi a5, 4 + simcall + movi a4, 1b + l32i a2, a4, 0 +#endif +.endm + #define glue(a, b) _glue(a, b) #define _glue(a, b) a ## b diff --git a/tests/tcg/xtensa/test_fp0_arith.S b/tests/tcg/xtensa/test_fp0_arith.S new file mode 100644 index 0000000000..253d033a33 --- /dev/null +++ b/tests/tcg/xtensa/test_fp0_arith.S @@ -0,0 +1,173 @@ +#include "macros.inc" + +test_suite fp0_arith + +#if XCHAL_HAVE_FP + +.macro movfp fr, v + movi a2, \v + wfr \fr, a2 +.endm + +.macro check_res fr, r + rfr a2, \fr + dump a2 + movi a3, \r + assert eq, a2, a3 + rur a2, fsr + assert eqi, a2, 0 +.endm + +.macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r + movi a2, 0 + wur a2, fsr + movfp \fr0, \v0 + movfp \fr1, \v1 + \op \fr2, \fr0, \fr1 + check_res \fr2, \r +.endm + +.macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r + movi a2, 0 + wur a2, fsr + movfp \fr0, \v0 + movfp \fr1, \v1 + movfp \fr2, \v2 + \op \fr0, \fr1, \fr2 + check_res \fr3, \r +.endm + +.macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r + movi a2, \rm + wur a2, fcr + test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r + movi a2, (\rm) | 0x7c + wur a2, fcr + test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r +.endm + +.macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r + movi a2, \rm + wur a2, fcr + test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r + movi a2, (\rm) | 0x7c + wur a2, fcr + test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r +.endm + +.macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3 + test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0 + test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1 + test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2 + test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3 +.endm + +.macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3 + test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0 + test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1 + test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2 + test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3 +.endm + +.macro test_op2_cpe op + set_vector kernel, 2f + movi a2, 0 + wsr a2, cpenable +1: + \op f2, f0, f1 + test_fail +2: + rsr a2, excvaddr + movi a3, 1b + assert eq, a2, a3 + rsr a2, exccause + movi a3, 32 + assert eq, a2, a3 + + set_vector kernel, 0 + movi a2, 1 + wsr a2, cpenable +.endm + +test add_s + movi a2, 1 + wsr a2, cpenable + + test_op2 add.s, f0, f1, f2, 0x3fc00000, 0x34400000, \ + 0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001 + test_op2 add.s, f3, f4, f5, 0x3fc00000, 0x34a00000, \ + 0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002 + + /* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */ + test_op2 add.s, f6, f7, f8, 0x7f7fffff, 0x7f7fffff, \ + 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff +test_end + +test add_s_inf + /* 1 + +inf = +inf */ + test_op2 add.s, f6, f7, f8, 0x3fc00000, 0x7f800000, \ + 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 + + /* +inf + -inf = default NaN */ + test_op2 add.s, f0, f1, f2, 0x7f800000, 0xff800000, \ + 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 +test_end + +test add_s_nan + /* 1 + NaN = NaN */ + test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \ + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001 + test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \ + 0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001 + + /* NaN1 + NaN2 = NaN1 */ + test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \ + 0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001 + test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \ + 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff + test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \ + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001 + test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \ + 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff +test_end + +test sub_s + test_op2 sub.s, f0, f1, f0, 0x3f800001, 0x33800000, \ + 0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000 + test_op2 sub.s, f0, f1, f1, 0x3f800002, 0x33800000, \ + 0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001 + + /* norm - norm = denorm */ + test_op2 sub.s, f6, f7, f8, 0x00800001, 0x00800000, \ + 0x00000001, 0x00000001, 0x00000001, 0x00000001 +test_end + +test mul_s + test_op2 mul.s, f0, f1, f2, 0x3f800001, 0x3f800001, \ + 0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002 + + /* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */ + test_op2 mul.s, f6, f7, f8, 0x7f000000, 0x7f000000, \ + 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff + /* min norm * min norm = 0/denorm */ + test_op2 mul.s, f6, f7, f8, 0x00800001, 0x00800000, \ + 0x00000000, 0x00000000, 0x00000001, 0x00000000 + + /* inf * 0 = default NaN */ + test_op2 mul.s, f6, f7, f8, 0x7f800000, 0x00000000, \ + 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 +test_end + +test madd_s + test_op3 madd.s, f0, f1, f2, f0, 0, 0x3f800001, 0x3f800001, \ + 0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002 +test_end + +test msub_s + test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \ + 0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001 +test_end + +#endif + +test_suite_end From 710b15f0415e95110346b5cbed83e0ea58cc3657 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sat, 8 Sep 2012 06:42:06 +0400 Subject: [PATCH 38/40] tests/tcg/xtensa: add FP0 group conversion tests Test conversions for normal, NaN and Inf arguments. Signed-off-by: Max Filippov --- tests/tcg/xtensa/Makefile | 1 + tests/tcg/xtensa/test_fp0_conv.S | 304 +++++++++++++++++++++++++++++++ 2 files changed, 305 insertions(+) create mode 100644 tests/tcg/xtensa/test_fp0_conv.S diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index eea269a36e..b1d9953f67 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -40,6 +40,7 @@ TESTCASES += test_extui.tst TESTCASES += test_fail.tst TESTCASES += test_flix.tst TESTCASES += test_fp0_arith.tst +TESTCASES += test_fp0_conv.tst TESTCASES += test_interrupt.tst TESTCASES += test_loop.tst TESTCASES += test_lsc.tst diff --git a/tests/tcg/xtensa/test_fp0_conv.S b/tests/tcg/xtensa/test_fp0_conv.S new file mode 100644 index 0000000000..147e3d5062 --- /dev/null +++ b/tests/tcg/xtensa/test_fp0_conv.S @@ -0,0 +1,304 @@ +#include "macros.inc" + +test_suite fp0_conv + +#if XCHAL_HAVE_FP + +.macro movfp fr, v + movi a2, \v + wfr \fr, a2 +.endm + +.macro test_ftoi_ex op, r0, fr0, v, c, r + movi a2, 0 + wur a2, fsr + movfp \fr0, \v + \op \r0, \fr0, \c + dump \r0 + movi a3, \r + assert eq, \r0, a3 + rur a2, fsr + assert eqi, a2, 0 +.endm + +.macro test_ftoi op, r0, fr0, v, c, r + movi a2, 0 + wur a2, fcr + test_ftoi_ex \op, \r0, \fr0, \v, \c, \r + movi a2, 0x7c + wur a2, fcr + test_ftoi_ex \op, \r0, \fr0, \v, \c, \r +.endm + + +.macro test_itof_ex op, fr0, ar0, v, c, r + movi a2, 0 + wur a2, fsr + movi \ar0, \v + \op \fr0, \ar0, \c + + rfr a2, \fr0 + dump a2 + movi a3, \r + assert eq, a2, a3 + rur a2, fsr + assert eqi, a2, 0 +.endm + +.macro test_itof_rm op, fr0, ar0, v, c, rm, r + movi a2, \rm + wur a2, fcr + test_itof_ex \op, \fr0, \ar0, \v, \c, \r + movi a2, (\rm) | 0x7c + wur a2, fcr + test_itof_ex \op, \fr0, \ar0, \v, \c, \r +.endm + +.macro test_itof op, fr0, ar0, v, c, r0, r1, r2, r3 + test_itof_rm \op, \fr0, \ar0, \v, \c, 0, \r0 + test_itof_rm \op, \fr0, \ar0, \v, \c, 1, \r1 + test_itof_rm \op, \fr0, \ar0, \v, \c, 2, \r2 + test_itof_rm \op, \fr0, \ar0, \v, \c, 3, \r3 +.endm + +test round_s + movi a2, 1 + wsr a2, cpenable + + /* NaN */ + test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff + test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff + + /* -inf */ + test_ftoi round.s, a2, f0, 0xff800000, 0, 0x80000000 + + /* negative overflow */ + test_ftoi round.s, a2, f0, 0xceffffff, 1, 0x80000000 + test_ftoi round.s, a2, f0, 0xcf000000, 0, 0x80000000 + test_ftoi round.s, a2, f0, 0xceffffff, 0, 0x80000080 + + /* negative */ + test_ftoi round.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */ + test_ftoi round.s, a2, f0, 0xbfc00000, 0, -2 /* -1.5 */ + test_ftoi round.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */ + test_ftoi round.s, a2, f0, 0xbf800000, 0, -1 /* -1 */ + test_ftoi round.s, a2, f0, 0xbf400000, 0, -1 /* -0.75 */ + test_ftoi round.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */ + + /* positive */ + test_ftoi round.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */ + test_ftoi round.s, a2, f0, 0x3f400000, 0, 1 /* 0.75 */ + test_ftoi round.s, a2, f0, 0x3f800000, 0, 1 /* 1 */ + test_ftoi round.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */ + test_ftoi round.s, a2, f0, 0x3fc00000, 0, 2 /* 1.5 */ + test_ftoi round.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */ + + /* positive overflow */ + test_ftoi round.s, a2, f0, 0x4effffff, 0, 0x7fffff80 + test_ftoi round.s, a2, f0, 0x4f000000, 0, 0x7fffffff + test_ftoi round.s, a2, f0, 0x4effffff, 1, 0x7fffffff + + /* +inf */ + test_ftoi round.s, a2, f0, 0x7f800000, 0, 0x7fffffff + + /* NaN */ + test_ftoi round.s, a2, f0, 0x7f800001, 0, 0x7fffffff + test_ftoi round.s, a2, f0, 0x7fc00000, 0, 0x7fffffff +test_end + +test trunc_s + /* NaN */ + test_ftoi trunc.s, a2, f0, 0xffc00001, 0, 0x7fffffff + test_ftoi trunc.s, a2, f0, 0xff800001, 0, 0x7fffffff + + /* -inf */ + test_ftoi trunc.s, a2, f0, 0xff800000, 0, 0x80000000 + + /* negative overflow */ + test_ftoi trunc.s, a2, f0, 0xceffffff, 1, 0x80000000 + test_ftoi trunc.s, a2, f0, 0xcf000000, 0, 0x80000000 + test_ftoi trunc.s, a2, f0, 0xceffffff, 0, 0x80000080 + + /* negative */ + test_ftoi trunc.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */ + test_ftoi trunc.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */ + test_ftoi trunc.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */ + test_ftoi trunc.s, a2, f0, 0xbf800000, 0, -1 /* -1 */ + test_ftoi trunc.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */ + test_ftoi trunc.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */ + + /* positive */ + test_ftoi trunc.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */ + test_ftoi trunc.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */ + test_ftoi trunc.s, a2, f0, 0x3f800000, 0, 1 /* 1 */ + test_ftoi trunc.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */ + test_ftoi trunc.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */ + test_ftoi trunc.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */ + + /* positive overflow */ + test_ftoi trunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80 + test_ftoi trunc.s, a2, f0, 0x4f000000, 0, 0x7fffffff + test_ftoi trunc.s, a2, f0, 0x4effffff, 1, 0x7fffffff + + /* +inf */ + test_ftoi trunc.s, a2, f0, 0x7f800000, 0, 0x7fffffff + + /* NaN */ + test_ftoi trunc.s, a2, f0, 0x7f800001, 0, 0x7fffffff + test_ftoi trunc.s, a2, f0, 0x7fc00000, 0, 0x7fffffff +test_end + +test floor_s + /* NaN */ + test_ftoi floor.s, a2, f0, 0xffc00001, 0, 0x7fffffff + test_ftoi floor.s, a2, f0, 0xff800001, 0, 0x7fffffff + + /* -inf */ + test_ftoi floor.s, a2, f0, 0xff800000, 0, 0x80000000 + + /* negative overflow */ + test_ftoi floor.s, a2, f0, 0xceffffff, 1, 0x80000000 + test_ftoi floor.s, a2, f0, 0xcf000000, 0, 0x80000000 + test_ftoi floor.s, a2, f0, 0xceffffff, 0, 0x80000080 + + /* negative */ + test_ftoi floor.s, a2, f0, 0xbfa00000, 1, -3 /* -1.25 * 2 */ + test_ftoi floor.s, a2, f0, 0xbfc00000, 0, -2 /* -1.5 */ + test_ftoi floor.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */ + test_ftoi floor.s, a2, f0, 0xbf800000, 0, -1 /* -1 */ + test_ftoi floor.s, a2, f0, 0xbf400000, 0, -1 /* -0.75 */ + test_ftoi floor.s, a2, f0, 0xbf000000, 0, -1 /* -0.5 */ + + /* positive */ + test_ftoi floor.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */ + test_ftoi floor.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */ + test_ftoi floor.s, a2, f0, 0x3f800000, 0, 1 /* 1 */ + test_ftoi floor.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */ + test_ftoi floor.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */ + test_ftoi floor.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */ + + /* positive overflow */ + test_ftoi floor.s, a2, f0, 0x4effffff, 0, 0x7fffff80 + test_ftoi floor.s, a2, f0, 0x4f000000, 0, 0x7fffffff + test_ftoi floor.s, a2, f0, 0x4effffff, 1, 0x7fffffff + + /* +inf */ + test_ftoi floor.s, a2, f0, 0x7f800000, 0, 0x7fffffff + + /* NaN */ + test_ftoi floor.s, a2, f0, 0x7f800001, 0, 0x7fffffff + test_ftoi floor.s, a2, f0, 0x7fc00000, 0, 0x7fffffff +test_end + +test ceil_s + /* NaN */ + test_ftoi ceil.s, a2, f0, 0xffc00001, 0, 0x7fffffff + test_ftoi ceil.s, a2, f0, 0xff800001, 0, 0x7fffffff + + /* -inf */ + test_ftoi ceil.s, a2, f0, 0xff800000, 0, 0x80000000 + + /* negative overflow */ + test_ftoi ceil.s, a2, f0, 0xceffffff, 1, 0x80000000 + test_ftoi ceil.s, a2, f0, 0xcf000000, 0, 0x80000000 + test_ftoi ceil.s, a2, f0, 0xceffffff, 0, 0x80000080 + + /* negative */ + test_ftoi ceil.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */ + test_ftoi ceil.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */ + test_ftoi ceil.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */ + test_ftoi ceil.s, a2, f0, 0xbf800000, 0, -1 /* -1 */ + test_ftoi ceil.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */ + test_ftoi ceil.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */ + + /* positive */ + test_ftoi ceil.s, a2, f0, 0x3f000000, 0, 1 /* 0.5 */ + test_ftoi ceil.s, a2, f0, 0x3f400000, 0, 1 /* 0.75 */ + test_ftoi ceil.s, a2, f0, 0x3f800000, 0, 1 /* 1 */ + test_ftoi ceil.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */ + test_ftoi ceil.s, a2, f0, 0x3fc00000, 0, 2 /* 1.5 */ + test_ftoi ceil.s, a2, f0, 0x3fa00000, 1, 3 /* 1.25 * 2 */ + + /* positive overflow */ + test_ftoi ceil.s, a2, f0, 0x4effffff, 0, 0x7fffff80 + test_ftoi ceil.s, a2, f0, 0x4f000000, 0, 0x7fffffff + test_ftoi ceil.s, a2, f0, 0x4effffff, 1, 0x7fffffff + + /* +inf */ + test_ftoi ceil.s, a2, f0, 0x7f800000, 0, 0x7fffffff + + /* NaN */ + test_ftoi ceil.s, a2, f0, 0x7f800001, 0, 0x7fffffff + test_ftoi ceil.s, a2, f0, 0x7fc00000, 0, 0x7fffffff +test_end + +test utrunc_s + /* NaN */ + test_ftoi utrunc.s, a2, f0, 0xffc00001, 0, 0xffffffff + test_ftoi utrunc.s, a2, f0, 0xff800001, 0, 0xffffffff + + /* -inf */ + test_ftoi utrunc.s, a2, f0, 0xff800000, 0, 0x80000000 + + /* negative overflow */ + test_ftoi utrunc.s, a2, f0, 0xceffffff, 1, 0x80000000 + test_ftoi utrunc.s, a2, f0, 0xcf000000, 0, 0x80000000 + test_ftoi utrunc.s, a2, f0, 0xceffffff, 0, 0x80000080 + + /* negative */ + test_ftoi utrunc.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */ + test_ftoi utrunc.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */ + test_ftoi utrunc.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */ + test_ftoi utrunc.s, a2, f0, 0xbf800000, 0, -1 /* -1 */ + test_ftoi utrunc.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */ + test_ftoi utrunc.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */ + + /* positive */ + test_ftoi utrunc.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */ + test_ftoi utrunc.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */ + test_ftoi utrunc.s, a2, f0, 0x3f800000, 0, 1 /* 1 */ + test_ftoi utrunc.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */ + test_ftoi utrunc.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */ + test_ftoi utrunc.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */ + + /* positive overflow */ + test_ftoi utrunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80 + test_ftoi utrunc.s, a2, f0, 0x4f000000, 0, 0x80000000 + test_ftoi utrunc.s, a2, f0, 0x4effffff, 1, 0xffffff00 + test_ftoi utrunc.s, a2, f0, 0x4f800000, 1, 0xffffffff + + /* +inf */ + test_ftoi utrunc.s, a2, f0, 0x7f800000, 0, 0xffffffff + + /* NaN */ + test_ftoi utrunc.s, a2, f0, 0x7f800001, 0, 0xffffffff + test_ftoi utrunc.s, a2, f0, 0x7fc00000, 0, 0xffffffff +test_end + +test float_s + test_itof float.s, f0, a2, -1, 0, \ + 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000 + test_itof float.s, f0, a2, 0, 0, 0, 0, 0, 0 + test_itof float.s, f0, a2, 1, 1, \ + 0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000 + test_itof float.s, f0, a2, 1, 0, \ + 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + test_itof float.s, f0, a2, 0x7fffffff, 0, \ + 0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff +test_end + +test ufloat_s + test_itof ufloat.s, f0, a2, 0, 0, 0, 0, 0, 0 + test_itof ufloat.s, f0, a2, 1, 1, \ + 0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000 + test_itof ufloat.s, f0, a2, 1, 0, \ + 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + test_itof ufloat.s, f0, a2, 0x7fffffff, 0, \ + 0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff + test_itof ufloat.s, f0, a2, 0xffffffff, 0, \ + 0x4f800000, 0x4f7fffff, 0x4f800000, 0x4f7fffff +test_end + +#endif + +test_suite_end From fd78bc55a44feecb385fa36cd149dbdc3110404b Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sun, 9 Sep 2012 04:03:49 +0400 Subject: [PATCH 39/40] tests/tcg/xtensa: add FP1 group tests Test comparisons and conditional move operations. Signed-off-by: Max Filippov --- tests/tcg/xtensa/Makefile | 1 + tests/tcg/xtensa/test_fp1.S | 141 ++++++++++++++++++++++++++++++++++++ 2 files changed, 142 insertions(+) create mode 100644 tests/tcg/xtensa/test_fp1.S diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index b1d9953f67..2b323adb8d 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -41,6 +41,7 @@ TESTCASES += test_fail.tst TESTCASES += test_flix.tst TESTCASES += test_fp0_arith.tst TESTCASES += test_fp0_conv.tst +TESTCASES += test_fp1.tst TESTCASES += test_interrupt.tst TESTCASES += test_loop.tst TESTCASES += test_lsc.tst diff --git a/tests/tcg/xtensa/test_fp1.S b/tests/tcg/xtensa/test_fp1.S new file mode 100644 index 0000000000..6e182e5964 --- /dev/null +++ b/tests/tcg/xtensa/test_fp1.S @@ -0,0 +1,141 @@ +#include "macros.inc" + +test_suite fp1 + +#if XCHAL_HAVE_FP + +.macro movfp fr, v + movi a2, \v + wfr \fr, a2 +.endm + +.macro test_ord_ex op, br, fr0, fr1, v0, v1, r + movi a2, 0 + wur a2, fsr + movfp \fr0, \v0 + movfp \fr1, \v1 + \op \br, \fr0, \fr1 + movi a2, 0 + movi a3, 1 + movt a2, a3, \br + assert eqi, a2, \r + rur a2, fsr + assert eqi, a2, 0 +.endm + +.macro test_ord op, br, fr0, fr1, v0, v1, r + movi a2, 0 + wur a2, fcr + test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r + movi a2, 0x7c + wur a2, fcr + test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r +.endm + +.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI + test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa + test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab + test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba + test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI + test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa + test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN + test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN + test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN + test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN + test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na + test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na + test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na + test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na + test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II + test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN + test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI +.endm + +test un_s + movi a2, 1 + wsr a2, cpenable + test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 +test_end + +test oeq_s + test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0 +test_end + +test ueq_s + test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1 +test_end + +test olt_s + test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 +test_end + +test ult_s + test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1 +test_end + +test ole_s + test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0 +test_end + +test ule_s + test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1 +test_end + +.macro test_cond op, fr0, fr1, cr, v0, v1, r + movfp \fr0, \v0 + movfp \fr1, \v1 + \op \fr0, \fr1, \cr + rfr a2, \fr0 + movi a3, \r + assert eq, a2, a3 +.endm + +test moveqz_s + movi a3, 0 + test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000 + movi a3, 1 + test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0 +test_end + +test movnez_s + movi a3, 0 + test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0 + movi a3, 1 + test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000 +test_end + +test movltz_s + movi a3, -1 + test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000 + movi a3, 0 + test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0 + movi a3, 1 + test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0 +test_end + +test movgez_s + movi a3, -1 + test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0 + movi a3, 0 + test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000 + movi a3, 1 + test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000 +test_end + +test movf_s + olt.s b0, f0, f0 + test_cond movf.s, f0, f1, b0, 0, 0x3f800000, 0x3f800000 + ueq.s b0, f0, f0 + test_cond movf.s, f0, f1, b0, 0, 0x3f800000, 0 +test_end + +test movt_s + ueq.s b0, f0, f0 + test_cond movt.s, f0, f1, b0, 0, 0x3f800000, 0x3f800000 + olt.s b0, f0, f0 + test_cond movt.s, f0, f1, b0, 0, 0x3f800000, 0 +test_end + +#endif + +test_suite_end From de0cebd93089ff2ebf2ebf9d287381eb73cbb9aa Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Fri, 31 Aug 2018 18:35:13 -0700 Subject: [PATCH 40/40] tests/tcg/xtensa: add FPU2000 coprocessor tests Signed-off-by: Max Filippov --- tests/tcg/xtensa/Makefile | 1 + tests/tcg/xtensa/test_fp_cpenable.S | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 tests/tcg/xtensa/test_fp_cpenable.S diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index 2b323adb8d..2bd4491769 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -42,6 +42,7 @@ TESTCASES += test_flix.tst TESTCASES += test_fp0_arith.tst TESTCASES += test_fp0_conv.tst TESTCASES += test_fp1.tst +TESTCASES += test_fp_cpenable.tst TESTCASES += test_interrupt.tst TESTCASES += test_loop.tst TESTCASES += test_lsc.tst diff --git a/tests/tcg/xtensa/test_fp_cpenable.S b/tests/tcg/xtensa/test_fp_cpenable.S new file mode 100644 index 0000000000..882bb2f3ce --- /dev/null +++ b/tests/tcg/xtensa/test_fp_cpenable.S @@ -0,0 +1,27 @@ +#include "macros.inc" + +test_suite fp_cpenable + +#if XCHAL_HAVE_FP + +test rur + set_vector kernel, 2f + movi a2, 0 + wsr a2, cpenable + isync +1: + rur a2, fsr + //wfr f0, a2 + test_fail +2: + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + movi a2, 32 + rsr a3, exccause + assert eq, a2, a3 +test_end + +#endif + +test_suite_end