RTC: Add divider reset support
The first update cycle begins one-half seconds after divider reset is removed. This feature is useful for testing. Signed-off-by: Yang Zhang <yang.z.zhang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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@ -83,6 +83,12 @@ static void rtc_update_time(RTCState *s);
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static void rtc_set_cmos(RTCState *s);
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static inline int rtc_from_bcd(RTCState *s, int a);
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static inline bool rtc_running(RTCState *s)
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{
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return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
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(s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
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}
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static uint64_t get_guest_rtc_ns(RTCState *s)
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{
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uint64_t guest_rtc;
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@ -199,11 +205,15 @@ static void check_update_timer(RTCState *s)
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uint64_t next_update_time;
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uint64_t guest_nsec;
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/* From the data sheet: setting the SET bit does not prevent
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* interrupts from occurring! However, it will prevent an
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* alarm interrupt from occurring, because the time of day is
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* not updated.
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/* From the data sheet: "Holding the dividers in reset prevents
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* interrupts from operating, while setting the SET bit allows"
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* them to occur. However, it will prevent an alarm interrupt
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* from occurring, because the time of day is not updated.
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*/
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if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
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qemu_del_timer(s->update_timer);
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return;
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}
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if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
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(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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qemu_del_timer(s->update_timer);
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@ -268,6 +278,8 @@ static void rtc_update_timer(void *opaque)
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int32_t irqs = REG_C_UF;
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int32_t new_irqs;
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assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60);
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/* UIP might have been latched, update time and clear it. */
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rtc_update_time(s);
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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@ -312,12 +324,31 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
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case RTC_YEAR:
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s->cmos_data[s->cmos_index] = data;
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/* if in set mode, do not update the time */
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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if (rtc_running(s)) {
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rtc_set_time(s);
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check_update_timer(s);
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}
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break;
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case RTC_REG_A:
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if ((data & 0x60) == 0x60) {
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if (rtc_running(s)) {
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rtc_update_time(s);
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}
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/* What happens to UIP when divider reset is enabled is
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* unclear from the datasheet. Shouldn't matter much
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* though.
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*/
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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} else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
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(data & 0x70) <= 0x20) {
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/* when the divider reset is removed, the first update cycle
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* begins one-half second later*/
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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s->offset = 500000000;
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rtc_set_time(s);
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}
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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}
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/* UIP bit is read only */
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s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
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(s->cmos_data[RTC_REG_A] & REG_A_UIP);
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@ -327,7 +358,7 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
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case RTC_REG_B:
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if (data & REG_B_SET) {
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/* update cmos to when the rtc was stopping */
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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if (rtc_running(s)) {
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rtc_update_time(s);
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}
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/* set mode: reset UIP mode */
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@ -335,7 +366,8 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
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data &= ~REG_B_UIE;
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} else {
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/* if disabling set mode, update the time */
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if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
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(s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
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s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC;
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rtc_set_time(s);
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}
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@ -449,7 +481,7 @@ static int update_in_progress(RTCState *s)
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{
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int64_t guest_nsec;
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if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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if (!rtc_running(s)) {
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return 0;
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}
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if (qemu_timer_pending(s->update_timer)) {
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@ -486,7 +518,7 @@ static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
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case RTC_YEAR:
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/* if not in set mode, calibrate cmos before
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* reading*/
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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if (rtc_running(s)) {
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rtc_update_time(s);
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}
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ret = s->cmos_data[s->cmos_index];
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