Add tb_page_addr_t
The page tracking code in exec.c is used by both userspace and system emulation. Userspace emulation uses it to track virtual pages, and system emulation to track ram pages. Introduce a new type to hold this kind of address. Signed-off-by: Paul Brook <paul@codesourcery.com>
This commit is contained in:
Paul Brook
parent
376a790970
commit
41c1b1c9eb
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@ -125,12 +125,13 @@ static TranslationBlock *tb_find_slow(target_ulong pc,
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{
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TranslationBlock *tb, **ptb1;
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unsigned int h;
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target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
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tb_page_addr_t phys_pc, phys_page1, phys_page2;
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target_ulong virt_page2;
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tb_invalidated_flag = 0;
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/* find translated block using physical mappings */
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phys_pc = get_phys_addr_code(env, pc);
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phys_pc = get_page_addr_code(env, pc);
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phys_page1 = phys_pc & TARGET_PAGE_MASK;
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phys_page2 = -1;
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h = tb_phys_hash_func(phys_pc);
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@ -147,7 +148,7 @@ static TranslationBlock *tb_find_slow(target_ulong pc,
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if (tb->page_addr[1] != -1) {
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virt_page2 = (pc & TARGET_PAGE_MASK) +
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TARGET_PAGE_SIZE;
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phys_page2 = get_phys_addr_code(env, virt_page2);
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phys_page2 = get_page_addr_code(env, virt_page2);
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if (tb->page_addr[1] == phys_page2)
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goto found;
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} else {
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25
exec-all.h
25
exec-all.h
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@ -25,6 +25,15 @@
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/* allow to see translation results - the slowdown should be negligible, so we leave it */
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#define DEBUG_DISAS
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/* Page tracking code uses ram addresses in system mode, and virtual
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addresses in userspace mode. Define tb_page_addr_t to be an appropriate
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type. */
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#if defined(CONFIG_USER_ONLY)
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typedef target_ulong tb_page_addr_t;
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#else
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typedef ram_addr_t tb_page_addr_t;
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#endif
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/* is_jmp field values */
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#define DISAS_NEXT 0 /* next instruction can be analyzed */
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#define DISAS_JUMP 1 /* only pc was modified dynamically */
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@ -81,7 +90,7 @@ TranslationBlock *tb_gen_code(CPUState *env,
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void cpu_exec_init(CPUState *env);
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void QEMU_NORETURN cpu_loop_exit(void);
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int page_unprotect(target_ulong address, unsigned long pc, void *puc);
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void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
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void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
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int is_cpu_write_access);
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void tb_invalidate_page_range(target_ulong start, target_ulong end);
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void tlb_flush_page(CPUState *env, target_ulong addr);
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@ -136,7 +145,7 @@ struct TranslationBlock {
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/* first and second physical page containing code. The lower bit
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of the pointer tells the index in page_next[] */
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struct TranslationBlock *page_next[2];
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target_ulong page_addr[2];
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tb_page_addr_t page_addr[2];
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/* the following data are used to directly call another TB from
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the code of this one. */
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@ -170,7 +179,7 @@ static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
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| (tmp & TB_JMP_ADDR_MASK));
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}
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static inline unsigned int tb_phys_hash_func(unsigned long pc)
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static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
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{
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return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
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}
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@ -178,9 +187,9 @@ static inline unsigned int tb_phys_hash_func(unsigned long pc)
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TranslationBlock *tb_alloc(target_ulong pc);
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void tb_free(TranslationBlock *tb);
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void tb_flush(CPUState *env);
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void tb_link_phys(TranslationBlock *tb,
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target_ulong phys_pc, target_ulong phys_page2);
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void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
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void tb_link_page(TranslationBlock *tb,
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tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
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void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
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extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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extern uint8_t *code_gen_ptr;
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@ -305,7 +314,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
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#endif
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#if defined(CONFIG_USER_ONLY)
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static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
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static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
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{
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return addr;
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}
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@ -313,7 +322,7 @@ static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
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/* NOTE: this function can trigger an exception */
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/* NOTE2: the returned address is not exactly the physical address: it
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is the offset relative to phys_ram_base */
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static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
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static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
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{
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int mmu_idx, page_index, pd;
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void *p;
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57
exec.c
57
exec.c
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@ -135,16 +135,14 @@ typedef struct PageDesc {
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#endif
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} PageDesc;
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typedef struct PhysPageDesc {
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/* offset in host memory of the page + io_index in the low bits */
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ram_addr_t phys_offset;
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ram_addr_t region_offset;
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} PhysPageDesc;
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/* In system mode we want L1_MAP to be based on physical addresses,
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/* In system mode we want L1_MAP to be based on ram offsets,
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while in user mode we want it to be based on virtual addresses. */
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#if !defined(CONFIG_USER_ONLY)
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#if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
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# define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS
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#else
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# define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS
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#endif
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#else
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# define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS
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#endif
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@ -188,6 +186,12 @@ unsigned long qemu_host_page_mask;
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static void *l1_map[V_L1_SIZE];
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#if !defined(CONFIG_USER_ONLY)
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typedef struct PhysPageDesc {
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/* offset in host memory of the page + io_index in the low bits */
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ram_addr_t phys_offset;
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ram_addr_t region_offset;
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} PhysPageDesc;
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/* This is a multi-level map on the physical address space.
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The bottom level has pointers to PhysPageDesc. */
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static void *l1_phys_map[P_L1_SIZE];
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@ -301,8 +305,12 @@ static void page_init(void)
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#endif
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}
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static PageDesc *page_find_alloc(target_ulong index, int alloc)
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static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
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{
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PageDesc *pd;
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void **lp;
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int i;
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#if defined(CONFIG_USER_ONLY)
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/* We can't use qemu_malloc because it may recurse into a locked mutex.
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Neither can we record the new pages we reserve while allocating a
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@ -328,10 +336,6 @@ static PageDesc *page_find_alloc(target_ulong index, int alloc)
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do { P = qemu_mallocz(SIZE); } while (0)
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#endif
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PageDesc *pd;
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void **lp;
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int i;
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/* Level 1. Always allocated. */
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lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1));
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@ -374,7 +378,7 @@ static PageDesc *page_find_alloc(target_ulong index, int alloc)
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return pd + (index & (L2_SIZE - 1));
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}
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static inline PageDesc *page_find(target_ulong index)
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static inline PageDesc *page_find(tb_page_addr_t index)
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{
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return page_find_alloc(index, 0);
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}
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@ -791,12 +795,12 @@ static inline void tb_reset_jump(TranslationBlock *tb, int n)
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tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
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}
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void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
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void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
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{
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CPUState *env;
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PageDesc *p;
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unsigned int h, n1;
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target_phys_addr_t phys_pc;
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tb_page_addr_t phys_pc;
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TranslationBlock *tb1, *tb2;
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/* remove the TB from the hash list */
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@ -908,10 +912,11 @@ TranslationBlock *tb_gen_code(CPUState *env,
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{
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TranslationBlock *tb;
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uint8_t *tc_ptr;
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target_ulong phys_pc, phys_page2, virt_page2;
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tb_page_addr_t phys_pc, phys_page2;
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target_ulong virt_page2;
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int code_gen_size;
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phys_pc = get_phys_addr_code(env, pc);
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phys_pc = get_page_addr_code(env, pc);
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tb = tb_alloc(pc);
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if (!tb) {
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/* flush must be done */
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@ -933,9 +938,9 @@ TranslationBlock *tb_gen_code(CPUState *env,
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virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
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phys_page2 = -1;
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if ((pc & TARGET_PAGE_MASK) != virt_page2) {
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phys_page2 = get_phys_addr_code(env, virt_page2);
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phys_page2 = get_page_addr_code(env, virt_page2);
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}
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tb_link_phys(tb, phys_pc, phys_page2);
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tb_link_page(tb, phys_pc, phys_page2);
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return tb;
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}
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@ -944,12 +949,12 @@ TranslationBlock *tb_gen_code(CPUState *env,
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the same physical page. 'is_cpu_write_access' should be true if called
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from a real cpu write access: the virtual CPU will exit the current
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TB if code is modified inside this TB. */
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void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
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void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
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int is_cpu_write_access)
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{
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TranslationBlock *tb, *tb_next, *saved_tb;
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CPUState *env = cpu_single_env;
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target_ulong tb_start, tb_end;
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tb_page_addr_t tb_start, tb_end;
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PageDesc *p;
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int n;
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#ifdef TARGET_HAS_PRECISE_SMC
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@ -1051,7 +1056,7 @@ void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t
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}
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/* len must be <= 8 and start must be a multiple of len */
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static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
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static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len)
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{
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PageDesc *p;
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int offset, b;
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@ -1078,7 +1083,7 @@ static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int le
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}
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#if !defined(CONFIG_SOFTMMU)
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static void tb_invalidate_phys_page(target_phys_addr_t addr,
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static void tb_invalidate_phys_page(tb_page_addr_t addr,
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unsigned long pc, void *puc)
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{
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TranslationBlock *tb;
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@ -1140,7 +1145,7 @@ static void tb_invalidate_phys_page(target_phys_addr_t addr,
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/* add the tb in the target page and protect it if necessary */
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static inline void tb_alloc_page(TranslationBlock *tb,
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unsigned int n, target_ulong page_addr)
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unsigned int n, tb_page_addr_t page_addr)
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{
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PageDesc *p;
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TranslationBlock *last_first_tb;
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@ -1221,8 +1226,8 @@ void tb_free(TranslationBlock *tb)
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/* add a new TB and link it to the physical page tables. phys_page2 is
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(-1) to indicate that only one page contains the TB. */
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void tb_link_phys(TranslationBlock *tb,
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target_ulong phys_pc, target_ulong phys_page2)
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void tb_link_page(TranslationBlock *tb,
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tb_page_addr_t phys_pc, tb_page_addr_t phys_page2)
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{
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unsigned int h;
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TranslationBlock **ptb;
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