arm: Implement PMCCNTR 32b read-modify-write
The register is now 64bit, however a 32 bit write to the register should leave the higher bits unchanged. The open coded write handler does not implement this, so we need to read-modify-write accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Alistair Francis <alistair23@gmail.com> Message-id: ec350573424bb2adc1701c3b9278d26598e2f2d1.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -623,6 +623,15 @@ static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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}
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env->cp15.c15_ccnt = total_ticks - value;
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}
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static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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uint64_t cur_val = pmccntr_read(env, NULL);
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pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
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}
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#endif
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static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -754,7 +763,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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#ifndef CONFIG_USER_ONLY
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{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
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.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
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.readfn = pmccntr_read, .writefn = pmccntr_write,
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.readfn = pmccntr_read, .writefn = pmccntr_write32,
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.accessfn = pmreg_access },
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#endif
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{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
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