OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block

Browse Source 
The SSE-300 has a new register block CPU<N>_PWRCTRL.  There is one
instance of this per CPU in the system (so just one for the SSE-300),
and as well as the usual CIDR/PIDR ID registers it has just one
register, CPUPWRCFG.  This register allows the guest to configure
behaviour of the system in power-down and deep-sleep states.  Since
QEMU does not model those, we make the register a dummy
reads-as-written implementation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-21-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-02-19 14:45:53 +00:00
parent 370d75d935
commit 4239b31146
7 changed files with 200 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -747,6 +747,8 @@ F: hw/misc/iotkit-sysctl.c
F: include/hw/misc/iotkit-sysctl.h
F: hw/misc/iotkit-sysinfo.c
F: include/hw/misc/iotkit-sysinfo.h
F: hw/misc/armsse-cpu-pwrctrl.c
F: include/hw/misc/armsse-cpu-pwrctrl.h
F: hw/misc/armsse-cpuid.c
F: include/hw/misc/armsse-cpuid.h
F: hw/misc/armsse-mhu.c

1
hw/arm/Kconfig
View File

@ -505,6 +505,7 @@ config ARM11MPCORE
config ARMSSE
bool
select ARM_V7M
select ARMSSE_CPU_PWRCTRL
select ARMSSE_CPUID
select ARMSSE_MHU
select CMSDK_APB_TIMER

3
hw/misc/Kconfig
View File

@ -8,6 +8,9 @@ config ARMSSE_CPUID
config ARMSSE_MHU
bool
config ARMSSE_CPU_PWRCTRL
bool
config MAX111X
bool

149
hw/misc/armsse-cpu-pwrctrl.c Normal file
View File

@ -0,0 +1,149 @@
/*
* Arm SSE CPU PWRCTRL register block
*
* Copyright (c) 2021 Linaro Limited
* Written by Peter Maydell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or
* (at your option) any later version.
*/
/*
* This is a model of the "CPU<N>_PWRCTRL block" which is part of the
* Arm Corstone SSE-300 Example Subsystem and documented in
* https://developer.arm.com/documentation/101773/0000
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "trace.h"
#include "qapi/error.h"
#include "migration/vmstate.h"
#include "hw/sysbus.h"
#include "hw/registerfields.h"
#include "hw/misc/armsse-cpu-pwrctrl.h"
REG32(CPUPWRCFG, 0x0)
REG32(PID4, 0xfd0)
REG32(PID5, 0xfd4)
REG32(PID6, 0xfd8)
REG32(PID7, 0xfdc)
REG32(PID0, 0xfe0)
REG32(PID1, 0xfe4)
REG32(PID2, 0xfe8)
REG32(PID3, 0xfec)
REG32(CID0, 0xff0)
REG32(CID1, 0xff4)
REG32(CID2, 0xff8)
REG32(CID3, 0xffc)
/* PID/CID values */
static const int cpu_pwrctrl_id[] = {
0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
0x5a, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
};
static uint64_t pwrctrl_read(void *opaque, hwaddr offset, unsigned size)
{
ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(opaque);
uint64_t r;
switch (offset) {
case A_CPUPWRCFG:
r = s->cpupwrcfg;
break;
case A_PID4 ... A_CID3:
r = cpu_pwrctrl_id[(offset - A_PID4) / 4];
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"SSE CPU_PWRCTRL read: bad offset %x\n", (int)offset);
r = 0;
break;
}
trace_armsse_cpu_pwrctrl_read(offset, r, size);
return r;
}
static void pwrctrl_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(opaque);
trace_armsse_cpu_pwrctrl_write(offset, value, size);
switch (offset) {
case A_CPUPWRCFG:
qemu_log_mask(LOG_UNIMP,
"SSE CPU_PWRCTRL: CPUPWRCFG unimplemented\n");
s->cpupwrcfg = value;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"SSE CPU_PWRCTRL write: bad offset 0x%x\n", (int)offset);
break;
}
}
static const MemoryRegionOps pwrctrl_ops = {
.read = pwrctrl_read,
.write = pwrctrl_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
};
static void pwrctrl_reset(DeviceState *dev)
{
ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(dev);
s->cpupwrcfg = 0;
}
static const VMStateDescription pwrctrl_vmstate = {
.name = "armsse-cpu-pwrctrl",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(cpupwrcfg, ARMSSECPUPwrCtrl),
VMSTATE_END_OF_LIST()
},
};
static void pwrctrl_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(obj);
memory_region_init_io(&s->iomem, obj, &pwrctrl_ops,
s, "armsse-cpu-pwrctrl", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
}
static void pwrctrl_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = pwrctrl_reset;
dc->vmsd = &pwrctrl_vmstate;
}
static const TypeInfo pwrctrl_info = {
.name = TYPE_ARMSSE_CPU_PWRCTRL,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ARMSSECPUPwrCtrl),
.instance_init = pwrctrl_init,
.class_init = pwrctrl_class_init,
};
static void pwrctrl_register_types(void)
{
type_register_static(&pwrctrl_info);
}
type_init(pwrctrl_register_types);

1
hw/misc/meson.build
View File

@ -96,6 +96,7 @@ softmmu_ss.add(when: 'CONFIG_TZ_MSC', if_true: files('tz-msc.c'))
softmmu_ss.add(when: 'CONFIG_TZ_PPC', if_true: files('tz-ppc.c'))
softmmu_ss.add(when: 'CONFIG_IOTKIT_SECCTL', if_true: files('iotkit-secctl.c'))
softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSINFO', if_true: files('iotkit-sysinfo.c'))
softmmu_ss.add(when: 'CONFIG_ARMSSE_CPU_PWRCTRL', if_true: files('armsse-cpu-pwrctrl.c'))
softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c'))
softmmu_ss.add(when: 'CONFIG_ARMSSE_MHU', if_true: files('armsse-mhu.c'))

4
hw/misc/trace-events
View File

@ -186,6 +186,10 @@ iotkit_sysctl_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl
iotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
iotkit_sysctl_reset(void) "IoTKit SysCtl: reset"
# armsse-cpu-pwrctrl.c
armsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
armsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
# armsse-cpuid.c
armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"

40
include/hw/misc/armsse-cpu-pwrctrl.h Normal file
View File

@ -0,0 +1,40 @@
/*
* ARM SSE CPU PWRCTRL register block
*
* Copyright (c) 2021 Linaro Limited
* Written by Peter Maydell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or
* (at your option) any later version.
*/
/*
* This is a model of the "CPU<N>_PWRCTRL block" which is part of the
* Arm Corstone SSE-300 Example Subsystem and documented in
* https://developer.arm.com/documentation/101773/0000
*
* QEMU interface:
* + sysbus MMIO region 0: the register bank
*/
#ifndef HW_MISC_ARMSSE_CPU_PWRCTRL_H
#define HW_MISC_ARMSSE_CPU_PWRCTRL_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_ARMSSE_CPU_PWRCTRL "armsse-cpu-pwrctrl"
OBJECT_DECLARE_SIMPLE_TYPE(ARMSSECPUPwrCtrl, ARMSSE_CPU_PWRCTRL)
struct ARMSSECPUPwrCtrl {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t cpupwrcfg;
};
#endif