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target/sparc: Move basic arithmetic to decodetree

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Move ADD, AND, OR, XOR, SUB, ANDN, ORN, XORN.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-01 21:49:43 -07:00
parent 2da789ded5
commit 428881deba
2 changed files with 94 additions and 103 deletions
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12
target/sparc/insns.decode
View File

@ -29,6 +29,9 @@ CALL 01 i:s30
&r_r_ri rd rs1 rs2_or_imm imm:bool
@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
&r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
@r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc
{
[
STBAR 10 00000 101000 01111 0 0000000000000
@ -152,6 +155,15 @@ WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri
WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri
WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri
ADD 10 ..... 0.0000 ..... . ............. @r_r_ri_cc
AND 10 ..... 0.0001 ..... . ............. @r_r_ri_cc
OR 10 ..... 0.0010 ..... . ............. @r_r_ri_cc
XOR 10 ..... 0.0011 ..... . ............. @r_r_ri_cc
SUB 10 ..... 0.0100 ..... . ............. @r_r_ri_cc
ANDN 10 ..... 0.0101 ..... . ............. @r_r_ri_cc
ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc
XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc
Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{
# For v7, the entire simm13 field is present, but masked to 7 bits.

185
target/sparc/translate.c
View File

@ -4013,6 +4013,88 @@ static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a)
return false;
}
static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op,
void (*func)(TCGv, TCGv, TCGv),
void (*funci)(TCGv, TCGv, target_long))
{
TCGv dst, src1;
/* For simplicity, we under-decoded the rs2 form. */
if (!a->imm && a->rs2_or_imm & ~0x1f) {
return false;
}
if (a->cc) {
dst = cpu_cc_dst;
} else {
dst = gen_dest_gpr(dc, a->rd);
}
src1 = gen_load_gpr(dc, a->rs1);
if (a->imm || a->rs2_or_imm == 0) {
if (funci) {
funci(dst, src1, a->rs2_or_imm);
} else {
func(dst, src1, tcg_constant_tl(a->rs2_or_imm));
}
} else {
func(dst, src1, cpu_regs[a->rs2_or_imm]);
}
gen_store_gpr(dc, a->rd, dst);
if (a->cc) {
tcg_gen_movi_i32(cpu_cc_op, cc_op);
dc->cc_op = cc_op;
}
return advance_pc(dc);
}
static bool do_arith(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op,
void (*func)(TCGv, TCGv, TCGv),
void (*funci)(TCGv, TCGv, target_long),
void (*func_cc)(TCGv, TCGv, TCGv))
{
if (a->cc) {
return do_arith_int(dc, a, cc_op, func_cc, NULL);
}
return do_arith_int(dc, a, cc_op, func, funci);
}
static bool do_logic(DisasContext *dc, arg_r_r_ri_cc *a,
void (*func)(TCGv, TCGv, TCGv),
void (*funci)(TCGv, TCGv, target_long))
{
return do_arith_int(dc, a, CC_OP_LOGIC, func, funci);
}
TRANS(ADD, ALL, do_arith, a, CC_OP_ADD,
tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_add_cc)
TRANS(SUB, ALL, do_arith, a, CC_OP_SUB,
tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc)
TRANS(AND, ALL, do_logic, a, tcg_gen_and_tl, tcg_gen_andi_tl)
TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl)
TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL)
TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL)
TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL)
static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
{
/* OR with %g0 is the canonical alias for MOV. */
if (!a->cc && a->rs1 == 0) {
if (a->imm || a->rs2_or_imm == 0) {
gen_store_gpr(dc, a->rd, tcg_constant_tl(a->rs2_or_imm));
} else if (a->rs2_or_imm & ~0x1f) {
/* For simplicity, we under-decoded the rs2 form. */
return false;
} else {
gen_store_gpr(dc, a->rd, cpu_regs[a->rs2_or_imm]);
}
return advance_pc(dc);
}
return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl);
}
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@ -4361,43 +4443,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
default:
goto illegal_insn;
}
} else if (xop == 0x2) {
TCGv dst = gen_dest_gpr(dc, rd);
rs1 = GET_FIELD(insn, 13, 17);
if (rs1 == 0) {
/* clr/mov shortcut : or %g0, x, y -> mov x, y */
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_movi_tl(dst, simm);
gen_store_gpr(dc, rd, dst);
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
if (rs2 == 0) {
tcg_gen_movi_tl(dst, 0);
gen_store_gpr(dc, rd, dst);
} else {
cpu_src2 = gen_load_gpr(dc, rs2);
gen_store_gpr(dc, rd, cpu_src2);
}
}
} else {
cpu_src1 = get_src1(dc, insn);
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_ori_tl(dst, cpu_src1, simm);
gen_store_gpr(dc, rd, dst);
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
if (rs2 == 0) {
/* mov shortcut: or x, %g0, y -> mov x, y */
gen_store_gpr(dc, rd, cpu_src1);
} else {
cpu_src2 = gen_load_gpr(dc, rs2);
tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
gen_store_gpr(dc, rd, dst);
}
}
}
#ifdef TARGET_SPARC64
} else if (xop == 0x25) { /* sll, V9 sllx */
cpu_src1 = get_src1(dc, insn);
@ -4474,72 +4519,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
case 0x0: /* add */
if (xop & 0x10) {
gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
dc->cc_op = CC_OP_ADD;
} else {
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
}
break;
case 0x1: /* and */
tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
dc->cc_op = CC_OP_LOGIC;
}
break;
case 0x2: /* or */
tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
dc->cc_op = CC_OP_LOGIC;
}
break;
case 0x3: /* xor */
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
dc->cc_op = CC_OP_LOGIC;
}
break;
case 0x4: /* sub */
if (xop & 0x10) {
gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
dc->cc_op = CC_OP_SUB;
} else {
tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
}
break;
case 0x5: /* andn */
tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
dc->cc_op = CC_OP_LOGIC;
}
break;
case 0x6: /* orn */
tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
dc->cc_op = CC_OP_LOGIC;
}
break;
case 0x7: /* xorn */
tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
dc->cc_op = CC_OP_LOGIC;
}
break;
case 0x8: /* addx, V9 addc */
gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
(xop & 0x10));