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Support epoch of 1980 in RTC emulation for MIPS Magnum

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On the MIPS Magnum, the time that is held in the RTC's NVRAM should be
relative to midnight on 1980-01-01.  This patch adds an extra parameter
to rtc_init(), allowing different epochs to be used.  For the Magnum,
1980 is specified, and for all other machines, 2000 is specified.

I've not modified the handling of the century byte, as with an epoch of
1980 and a year of 2009, one could argue that it should hold either
0, 1, 19 or 20.  NT 3.50 on MIPS does not read the century byte.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6429 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2009-01-24 18:06:21 +00:00
parent e2fc836b18
commit 42fc73a1ce
7 changed files with 20 additions and 11 deletions
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16
hw/mc146818rtc.c
View File

@ -60,6 +60,7 @@ struct RTCState {
uint8_t cmos_data[128];
uint8_t cmos_index;
struct tm current_tm;
int base_year;
qemu_irq irq;
int it_shift;
/* periodic timer */
@ -235,12 +236,13 @@ static void rtc_set_time(RTCState *s)
tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
}
static void rtc_copy_date(RTCState *s)
{
const struct tm *tm = &s->current_tm;
int year;
s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
@ -256,7 +258,10 @@ static void rtc_copy_date(RTCState *s)
s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday + 1);
s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
year = (tm->tm_year - s->base_year) % 100;
if (year < 0)
year += 100;
s->cmos_data[RTC_YEAR] = to_bcd(s, year);
}
/* month is between 0 and 11. */
@ -522,7 +527,7 @@ static int rtc_load_td(QEMUFile *f, void *opaque, int version_id)
}
#endif
RTCState *rtc_init(int base, qemu_irq irq)
RTCState *rtc_init(int base, qemu_irq irq, int base_year)
{
RTCState *s;
@ -536,6 +541,7 @@ RTCState *rtc_init(int base, qemu_irq irq)
s->cmos_data[RTC_REG_C] = 0x00;
s->cmos_data[RTC_REG_D] = 0x80;
s->base_year = base_year;
rtc_set_date_from_host(s);
s->periodic_timer = qemu_new_timer(vm_clock,
@ -631,7 +637,8 @@ static CPUWriteMemoryFunc *rtc_mm_write[] = {
&cmos_mm_writel,
};
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
int base_year)
{
RTCState *s;
int io_memory;
@ -646,6 +653,7 @@ RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
s->cmos_data[RTC_REG_C] = 0x00;
s->cmos_data[RTC_REG_D] = 0x80;
s->base_year = base_year;
rtc_set_date_from_host(s);
s->periodic_timer = qemu_new_timer(vm_clock,

2
hw/mips_jazz.c
View File

@ -241,7 +241,7 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
fdctrl_init(rc4030[1], 0, 1, 0x80003000, fds);
/* Real time clock */
rtc_init(0x70, i8259[8]);
rtc_init(0x70, i8259[8], 1980);
s_rtc = cpu_register_io_memory(0, rtc_read, rtc_write, env);
cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);

2
hw/mips_malta.c
View File

@ -918,7 +918,7 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
/* Super I/O */
i8042_init(i8259[1], i8259[12], 0x60);
rtc_state = rtc_init(0x70, i8259[8]);
rtc_state = rtc_init(0x70, i8259[8], 2000);
serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
serial_init(0x2f8, i8259[3], 115200, serial_hds[1]);
if (parallel_hds[0])

2
hw/mips_r4k.c
View File

@ -235,7 +235,7 @@ void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
/* The PIC is attached to the MIPS CPU INT0 pin */
i8259 = i8259_init(env->irq[2]);
rtc_state = rtc_init(0x70, i8259[8]);
rtc_state = rtc_init(0x70, i8259[8], 2000);
/* Register 64 KB of ISA IO space at 0x14000000 */
isa_mmio_init(0x14000000, 0x00010000);

2
hw/pc.c
View File

@ -968,7 +968,7 @@ vga_bios_error:
}
}
rtc_state = rtc_init(0x70, i8259[8]);
rtc_state = rtc_init(0x70, i8259[8], 2000);
qemu_register_boot_set(pc_boot_set, rtc_state);

5
hw/pc.h
View File

@ -83,8 +83,9 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
typedef struct RTCState RTCState;
RTCState *rtc_init(int base, qemu_irq irq);
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
RTCState *rtc_init(int base, qemu_irq irq, int base_year);
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
int base_year);
void rtc_set_memory(RTCState *s, int addr, int val);
void rtc_set_date(RTCState *s, const struct tm *tm);
void cmos_set_s3_resume(void);

2
hw/ppc_prep.c
View File

@ -659,7 +659,7 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
vga_ram_size, 0, 0);
// openpic = openpic_init(0x00000000, 0xF0000000, 1);
// pit = pit_init(0x40, i8259[0]);
rtc_init(0x70, i8259[8]);
rtc_init(0x70, i8259[8], 2000);
serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
nb_nics1 = nb_nics;