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target/ppc: Do not clear MSR[ME] on MCE interrupts to supervisor

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Hardware clears the MSR[ME] bit when delivering a machine check
interrupt, so that is what QEMU does.

The spapr environment runs in supervisor mode though, and receives
machine check interrupts after they are processed by the hypervisor,
and MSR[ME] must always be enabled in supervisor mode (otherwise it
could checkstop the system). So MSR[ME] must not be cleared when
delivering machine checks to the supervisor.

The fix to prevent supervisor mode from modifying MSR[ME] also
prevented it from re-enabling the incorrectly cleared MSR[ME] bit
when returning from handling the interrupt. Before that fix, the
problem was not very noticable with well-behaved code. So the
Fixes tag is not strictly correct, but practically they go together.

Found by kvm-unit-tests machine check tests (not yet upstream).

Fixes: 678b6f1af7 ("target/ppc: Prevent supervisor from modifying MSR[ME]")
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-03-19 16:01:46 +10:00
parent ed399ade3c
commit 434531619f
1 changed files with 3 additions and 2 deletions
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5
target/ppc/excp_helper.c
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@ -1345,9 +1345,10 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
* clear (e.g., see FWNMI in PAPR). * clear (e.g., see FWNMI in PAPR).
*/ */
new_msr |= (target_ulong)MSR_HVB; new_msr |= (target_ulong)MSR_HVB;
/* HV machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
} }
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
msr |= env->error_code; msr |= env->error_code;
break; break;