hw/intc: Remove the Ibex PLIC
The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and instead use the SiFive PLIC. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis
parent
ef63100648
commit
434e7e0217
@ -1,307 +0,0 @@
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/*
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* QEMU RISC-V lowRISC Ibex PLIC
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*
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* Copyright (c) 2020 Western Digital
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*
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* Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/qdev-properties.h"
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#include "hw/core/cpu.h"
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#include "hw/boards.h"
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#include "hw/pci/msi.h"
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#include "target/riscv/cpu_bits.h"
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#include "target/riscv/cpu.h"
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#include "hw/intc/ibex_plic.h"
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#include "hw/irq.h"
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static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
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{
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uint32_t end = base + (num * 0x04);
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if (addr >= base && addr < end) {
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return true;
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}
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return false;
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}
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static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
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{
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int pending_num = irq / 32;
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if (!level) {
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/*
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* If the level is low make sure we clear the hidden_pending.
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*/
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s->hidden_pending[pending_num] &= ~(1 << (irq % 32));
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}
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if (s->claimed[pending_num] & 1 << (irq % 32)) {
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/*
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* The interrupt has been claimed, but not completed.
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* The pending bit can't be set.
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* Save the pending level for after the interrupt is completed.
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*/
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s->hidden_pending[pending_num] |= level << (irq % 32);
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} else {
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s->pending[pending_num] |= level << (irq % 32);
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}
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}
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static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
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{
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int i;
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uint32_t max_irq = 0;
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uint32_t max_prio = s->threshold;
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for (i = 0; i < s->pending_num; i++) {
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uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
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if (!(s->pending[i] & s->enable[i])) {
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/* No pending and enabled IRQ */
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continue;
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}
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if (s->priority[irq_num] > max_prio) {
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max_irq = irq_num;
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max_prio = s->priority[irq_num];
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}
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}
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if (max_irq) {
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s->claim = max_irq;
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return true;
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}
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return false;
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}
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static void ibex_plic_update(IbexPlicState *s)
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{
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int i;
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for (i = 0; i < s->num_cpus; i++) {
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qemu_set_irq(s->external_irqs[i], ibex_plic_irqs_pending(s, 0));
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}
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}
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static void ibex_plic_reset(DeviceState *dev)
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{
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IbexPlicState *s = IBEX_PLIC(dev);
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s->threshold = 0x00000000;
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s->claim = 0x00000000;
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}
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static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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IbexPlicState *s = opaque;
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int offset;
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uint32_t ret = 0;
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if (addr_between(addr, s->pending_base, s->pending_num)) {
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offset = (addr - s->pending_base) / 4;
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ret = s->pending[offset];
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} else if (addr_between(addr, s->source_base, s->source_num)) {
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qemu_log_mask(LOG_UNIMP,
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"%s: Interrupt source mode not supported\n", __func__);
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} else if (addr_between(addr, s->priority_base, s->priority_num)) {
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offset = (addr - s->priority_base) / 4;
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ret = s->priority[offset];
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} else if (addr_between(addr, s->enable_base, s->enable_num)) {
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offset = (addr - s->enable_base) / 4;
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ret = s->enable[offset];
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} else if (addr_between(addr, s->threshold_base, 1)) {
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ret = s->threshold;
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} else if (addr_between(addr, s->claim_base, 1)) {
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int pending_num = s->claim / 32;
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s->pending[pending_num] &= ~(1 << (s->claim % 32));
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/* Set the interrupt as claimed, but not completed */
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s->claimed[pending_num] |= 1 << (s->claim % 32);
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/* Return the current claimed interrupt */
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ret = s->claim;
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/* Clear the claimed interrupt */
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s->claim = 0x00000000;
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/* Update the interrupt status after the claim */
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ibex_plic_update(s);
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}
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return ret;
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}
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static void ibex_plic_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned int size)
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{
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IbexPlicState *s = opaque;
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if (addr_between(addr, s->pending_base, s->pending_num)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Pending registers are read only\n", __func__);
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} else if (addr_between(addr, s->source_base, s->source_num)) {
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qemu_log_mask(LOG_UNIMP,
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"%s: Interrupt source mode not supported\n", __func__);
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} else if (addr_between(addr, s->priority_base, s->priority_num)) {
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uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
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s->priority[irq] = value & 7;
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ibex_plic_update(s);
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} else if (addr_between(addr, s->enable_base, s->enable_num)) {
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uint32_t enable_reg = (addr - s->enable_base) / 4;
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s->enable[enable_reg] = value;
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} else if (addr_between(addr, s->threshold_base, 1)) {
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s->threshold = value & 3;
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} else if (addr_between(addr, s->claim_base, 1)) {
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if (s->claim == value) {
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/* Interrupt was completed */
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s->claim = 0;
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}
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if (s->claimed[value / 32] & 1 << (value % 32)) {
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int pending_num = value / 32;
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/* This value was already claimed, clear it. */
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s->claimed[pending_num] &= ~(1 << (value % 32));
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if (s->hidden_pending[pending_num] & (1 << (value % 32))) {
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/*
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* If the bit in hidden_pending is set then that means we
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* received an interrupt between claiming and completing
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* the interrupt that hasn't since been de-asserted.
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* On hardware this would trigger an interrupt, so let's
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* trigger one here as well.
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*/
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s->pending[pending_num] |= 1 << (value % 32);
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}
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}
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}
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ibex_plic_update(s);
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}
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static const MemoryRegionOps ibex_plic_ops = {
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.read = ibex_plic_read,
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.write = ibex_plic_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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static void ibex_plic_irq_request(void *opaque, int irq, int level)
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{
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IbexPlicState *s = opaque;
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ibex_plic_irqs_set_pending(s, irq, level > 0);
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ibex_plic_update(s);
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}
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static Property ibex_plic_properties[] = {
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DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
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DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
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DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
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DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
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DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
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DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
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DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
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DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
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DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
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DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
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DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
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DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void ibex_plic_init(Object *obj)
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{
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IbexPlicState *s = IBEX_PLIC(obj);
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memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
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TYPE_IBEX_PLIC, 0x400);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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}
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static void ibex_plic_realize(DeviceState *dev, Error **errp)
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{
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IbexPlicState *s = IBEX_PLIC(dev);
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int i;
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s->pending = g_new0(uint32_t, s->pending_num);
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s->hidden_pending = g_new0(uint32_t, s->pending_num);
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s->claimed = g_new0(uint32_t, s->pending_num);
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s->source = g_new0(uint32_t, s->source_num);
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s->priority = g_new0(uint32_t, s->priority_num);
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s->enable = g_new0(uint32_t, s->enable_num);
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qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
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s->external_irqs = g_malloc(sizeof(qemu_irq) * s->num_cpus);
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qdev_init_gpio_out(dev, s->external_irqs, s->num_cpus);
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/*
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* We can't allow the supervisor to control SEIP as this would allow the
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* supervisor to clear a pending external interrupt which will result in
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* a lost interrupt in the case a PLIC is attached. The SEIP bit must be
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* hardware controlled when a PLIC is attached.
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*/
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MachineState *ms = MACHINE(qdev_get_machine());
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unsigned int smp_cpus = ms->smp.cpus;
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for (i = 0; i < smp_cpus; i++) {
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RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
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if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
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error_report("SEIP already claimed");
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exit(1);
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}
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}
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msi_nonbroken = true;
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}
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static void ibex_plic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = ibex_plic_reset;
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device_class_set_props(dc, ibex_plic_properties);
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dc->realize = ibex_plic_realize;
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}
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static const TypeInfo ibex_plic_info = {
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.name = TYPE_IBEX_PLIC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IbexPlicState),
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.instance_init = ibex_plic_init,
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.class_init = ibex_plic_class_init,
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};
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static void ibex_plic_register_types(void)
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{
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type_register_static(&ibex_plic_info);
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}
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type_init(ibex_plic_register_types)
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@ -32,7 +32,6 @@ specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
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specific_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c'))
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specific_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c'))
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specific_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_gic.c', 'exynos4210_combiner.c'))
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specific_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_gic.c', 'exynos4210_combiner.c'))
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specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
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specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
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specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_plic.c'))
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specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))
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specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))
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specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_liointc.c'))
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specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_liointc.c'))
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specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c'))
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specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c'))
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