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target-riscv: support QMP dump-guest-memory 

Add the support needed for creating prstatus elf notes. This allows
us to use QMP dump-guest-memory.

Now ELF notes of RISC-V only contain prstatus elf notes.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 20210201124458.1248-2-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Yifei Jiang 2021-02-01 20:44:58 +08:00 committed by Alistair Francis
parent 454d1e7cf2
commit 43a9658889
5 changed files with 210 additions and 0 deletions
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202
target/riscv/arch_dump.c Normal file
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@ -0,0 +1,202 @@
/* Support for writing ELF notes for RISC-V architectures
*
* Copyright (C) 2021 Huawei Technologies Co., Ltd
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "elf.h"
#include "sysemu/dump.h"
/* struct user_regs_struct from arch/riscv/include/uapi/asm/ptrace.h */
struct riscv64_user_regs {
uint64_t pc;
uint64_t regs[31];
} QEMU_PACKED;
QEMU_BUILD_BUG_ON(sizeof(struct riscv64_user_regs) != 256);
/* struct elf_prstatus from include/linux/elfcore.h */
struct riscv64_elf_prstatus {
char pad1[32]; /* 32 == offsetof(struct elf_prstatus, pr_pid) */
uint32_t pr_pid;
char pad2[76]; /* 76 == offsetof(struct elf_prstatus, pr_reg) -
offsetof(struct elf_prstatus, pr_ppid) */
struct riscv64_user_regs pr_reg;
char pad3[8];
} QEMU_PACKED;
QEMU_BUILD_BUG_ON(sizeof(struct riscv64_elf_prstatus) != 376);
struct riscv64_note {
Elf64_Nhdr hdr;
char name[8]; /* align_up(sizeof("CORE"), 4) */
struct riscv64_elf_prstatus prstatus;
} QEMU_PACKED;
#define RISCV64_NOTE_HEADER_SIZE offsetof(struct riscv64_note, prstatus)
#define RISCV64_PRSTATUS_NOTE_SIZE \
(RISCV64_NOTE_HEADER_SIZE + sizeof(struct riscv64_elf_prstatus))
static void riscv64_note_init(struct riscv64_note *note, DumpState *s,
const char *name, Elf64_Word namesz,
Elf64_Word type, Elf64_Word descsz)
{
memset(note, 0, sizeof(*note));
note->hdr.n_namesz = cpu_to_dump32(s, namesz);
note->hdr.n_descsz = cpu_to_dump32(s, descsz);
note->hdr.n_type = cpu_to_dump32(s, type);
memcpy(note->name, name, namesz);
}
int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque)
{
struct riscv64_note note;
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
DumpState *s = opaque;
int ret, i = 0;
const char name[] = "CORE";
riscv64_note_init(&note, s, name, sizeof(name),
NT_PRSTATUS, sizeof(note.prstatus));
note.prstatus.pr_pid = cpu_to_dump32(s, cpuid);
note.prstatus.pr_reg.pc = cpu_to_dump64(s, env->pc);
for (i = 0; i < 31; i++) {
note.prstatus.pr_reg.regs[i] = cpu_to_dump64(s, env->gpr[i + 1]);
}
ret = f(&note, RISCV64_PRSTATUS_NOTE_SIZE, s);
if (ret < 0) {
return -1;
}
return ret;
}
struct riscv32_user_regs {
uint32_t pc;
uint32_t regs[31];
} QEMU_PACKED;
QEMU_BUILD_BUG_ON(sizeof(struct riscv32_user_regs) != 128);
struct riscv32_elf_prstatus {
char pad1[24]; /* 24 == offsetof(struct elf_prstatus, pr_pid) */
uint32_t pr_pid;
char pad2[44]; /* 44 == offsetof(struct elf_prstatus, pr_reg) -
offsetof(struct elf_prstatus, pr_ppid) */
struct riscv32_user_regs pr_reg;
char pad3[4];
} QEMU_PACKED;
QEMU_BUILD_BUG_ON(sizeof(struct riscv32_elf_prstatus) != 204);
struct riscv32_note {
Elf32_Nhdr hdr;
char name[8]; /* align_up(sizeof("CORE"), 4) */
struct riscv32_elf_prstatus prstatus;
} QEMU_PACKED;
#define RISCV32_NOTE_HEADER_SIZE offsetof(struct riscv32_note, prstatus)
#define RISCV32_PRSTATUS_NOTE_SIZE \
(RISCV32_NOTE_HEADER_SIZE + sizeof(struct riscv32_elf_prstatus))
static void riscv32_note_init(struct riscv32_note *note, DumpState *s,
const char *name, Elf32_Word namesz,
Elf32_Word type, Elf32_Word descsz)
{
memset(note, 0, sizeof(*note));
note->hdr.n_namesz = cpu_to_dump32(s, namesz);
note->hdr.n_descsz = cpu_to_dump32(s, descsz);
note->hdr.n_type = cpu_to_dump32(s, type);
memcpy(note->name, name, namesz);
}
int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque)
{
struct riscv32_note note;
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
DumpState *s = opaque;
int ret, i;
const char name[] = "CORE";
riscv32_note_init(&note, s, name, sizeof(name),
NT_PRSTATUS, sizeof(note.prstatus));
note.prstatus.pr_pid = cpu_to_dump32(s, cpuid);
note.prstatus.pr_reg.pc = cpu_to_dump32(s, env->pc);
for (i = 0; i < 31; i++) {
note.prstatus.pr_reg.regs[i] = cpu_to_dump32(s, env->gpr[i + 1]);
}
ret = f(&note, RISCV32_PRSTATUS_NOTE_SIZE, s);
if (ret < 0) {
return -1;
}
return ret;
}
int cpu_get_dump_info(ArchDumpInfo *info,
const GuestPhysBlockList *guest_phys_blocks)
{
RISCVCPU *cpu;
CPURISCVState *env;
if (first_cpu == NULL) {
return -1;
}
cpu = RISCV_CPU(first_cpu);
env = &cpu->env;
info->d_machine = EM_RISCV;
#if defined(TARGET_RISCV64)
info->d_class = ELFCLASS64;
#else
info->d_class = ELFCLASS32;
#endif
info->d_endian = (env->mstatus & MSTATUS_UBE) != 0
? ELFDATA2MSB : ELFDATA2LSB;
return 0;
}
ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
{
size_t note_size;
if (class == ELFCLASS64) {
note_size = RISCV64_PRSTATUS_NOTE_SIZE;
} else {
note_size = RISCV32_PRSTATUS_NOTE_SIZE;
}
return note_size * nr_cpus;
}

2
target/riscv/cpu.c
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@ -624,6 +624,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
cc->write_elf64_note = riscv_cpu_write_elf64_note;
cc->write_elf32_note = riscv_cpu_write_elf32_note;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;

4
target/riscv/cpu.h
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@ -323,6 +323,10 @@ extern const char * const riscv_intr_names[];
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque);
int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);

1
target/riscv/cpu_bits.h
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@ -368,6 +368,7 @@
#define MSTATUS_MIE 0x00000008
#define MSTATUS_UPIE 0x00000010
#define MSTATUS_SPIE 0x00000020
#define MSTATUS_UBE 0x00000040
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100
#define MSTATUS_MPP 0x00001800

1
target/riscv/meson.build
View File

@ -26,6 +26,7 @@ riscv_ss.add(files(
riscv_softmmu_ss = ss.source_set()
riscv_softmmu_ss.add(files(
'arch_dump.c',
'pmp.c',
'monitor.c',
'machine.c'