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tests/tcg/s390x: Test CLC with inaccessible second operand

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Add a small test to prevent regressions.

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231106093605.1349201-3-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Ilya Leoshkevich 2023-11-06 10:31:23 +01:00 committed by Thomas Huth
parent aba2ec341c
commit 43fecbe7a5
2 changed files with 49 additions and 0 deletions
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1
tests/tcg/s390x/Makefile.target
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@ -41,6 +41,7 @@ TESTS+=larl
TESTS+=mdeb
TESTS+=cgebra
TESTS+=clgebr
TESTS+=clc
cdsg: CFLAGS+=-pthread
cdsg: LDFLAGS+=-pthread

48
tests/tcg/s390x/clc.c Normal file
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@ -0,0 +1,48 @@
/*
* Test the CLC instruction.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <assert.h>
#include <signal.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
static void handle_sigsegv(int sig, siginfo_t *info, void *ucontext)
{
mcontext_t *mcontext = &((ucontext_t *)ucontext)->uc_mcontext;
if (mcontext->gregs[0] != 600) {
write(STDERR_FILENO, "bad r0\n", 7);
_exit(EXIT_FAILURE);
}
if (((mcontext->psw.mask >> 44) & 3) != 1) {
write(STDERR_FILENO, "bad cc\n", 7);
_exit(EXIT_FAILURE);
}
_exit(EXIT_SUCCESS);
}
int main(void)
{
register unsigned long r0 asm("r0");
unsigned long mem = 42, rhs = 500;
struct sigaction act;
int err;
memset(&act, 0, sizeof(act));
act.sa_sigaction = handle_sigsegv;
act.sa_flags = SA_SIGINFO;
err = sigaction(SIGSEGV, &act, NULL);
assert(err == 0);
r0 = 100;
asm("algr %[r0],%[rhs]\n"
"clc 0(8,%[mem]),0(0)\n" /* The 2nd operand will cause a SEGV. */
: [r0] "+r" (r0)
: [mem] "r" (&mem)
, [rhs] "r" (rhs)
: "cc", "memory");
return EXIT_FAILURE;
}