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target/arm: Mark PMULL, FMMLA as non-streaming

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Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-07-08 20:45:02 +05:30 committed by Peter Maydell
parent ca363d233f
commit 4464ee3634
2 changed files with 15 additions and 11 deletions
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2
target/arm/sme-fa64.decode
View File

@ -59,8 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result)
FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA
FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL
FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD
FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA

24
target/arm/translate-sve.c
View File

@ -6186,9 +6186,13 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
gen_helper_gvec_pmull_q, gen_helper_sve2_pmull_h, gen_helper_gvec_pmull_q, gen_helper_sve2_pmull_h,
NULL, gen_helper_sve2_pmull_d, NULL, gen_helper_sve2_pmull_d,
}; };
if (a->esz == 0
? !dc_isar_feature(aa64_sve2_pmull128, s) if (a->esz == 0) {
: !dc_isar_feature(aa64_sve, s)) { if (!dc_isar_feature(aa64_sve2_pmull128, s)) {
return false;
}
s->is_nonstreaming = true;
} else if (!dc_isar_feature(aa64_sve, s)) {
return false; return false;
} }
return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel); return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel);
@ -7125,10 +7129,12 @@ DO_ZPZZ_FP(FMINP, aa64_sve2, sve2_fminp_zpzz)
* SVE Integer Multiply-Add (unpredicated) * SVE Integer Multiply-Add (unpredicated)
*/ */
TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s, TRANS_FEAT_NONSTREAMING(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz,
a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR) gen_helper_fmmla_s, a->rd, a->rn, a->rm, a->ra,
TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d, 0, FPST_FPCR)
a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR) TRANS_FEAT_NONSTREAMING(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz,
gen_helper_fmmla_d, a->rd, a->rn, a->rm, a->ra,
0, FPST_FPCR)
static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = { static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
NULL, gen_helper_sve2_sqdmlal_zzzw_h, NULL, gen_helper_sve2_sqdmlal_zzzw_h,
@ -7301,8 +7307,8 @@ TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz, TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz,
gen_helper_gvec_bfdot_idx, a) gen_helper_gvec_bfdot_idx, a)
TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
gen_helper_gvec_bfmmla, a, 0) gen_helper_gvec_bfmmla, a, 0)
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
{ {