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target/loongarch: Implement LASX logic instructions

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This patch includes:
- XV{AND/OR/XOR/NOR/ANDN/ORN}.V;
- XV{AND/OR/XOR/NOR}I.B.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-35-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-09-14 10:26:22 +08:00
parent a59098e311
commit 4472a45a08
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
4 changed files with 48 additions and 18 deletions
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12
target/loongarch/disas.c
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@ -2029,6 +2029,18 @@ INSN_LASX(xvmsknz_b, vv)
INSN_LASX(xvldi, v_i)
INSN_LASX(xvand_v, vvv)
INSN_LASX(xvor_v, vvv)
INSN_LASX(xvxor_v, vvv)
INSN_LASX(xvnor_v, vvv)
INSN_LASX(xvandn_v, vvv)
INSN_LASX(xvorn_v, vvv)
INSN_LASX(xvandi_b, vv_i)
INSN_LASX(xvori_b, vv_i)
INSN_LASX(xvxori_b, vv_i)
INSN_LASX(xvnori_b, vv_i)
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)

38
target/loongarch/insn_trans/trans_vec.c.inc
View File

@ -3573,20 +3573,11 @@ static bool gen_vldi(DisasContext *ctx, arg_vldi *a, uint32_t oprsz)
TRANS(vldi, LSX, gen_vldi, 16)
TRANS(xvldi, LASX, gen_vldi, 32)
TRANS(vand_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_and)
TRANS(vor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_or)
TRANS(vxor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_xor)
TRANS(vnor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_nor)
static bool trans_vandn_v(DisasContext *ctx, arg_vvv *a)
static bool gen_vandn_v(DisasContext *ctx, arg_vvv *a, uint32_t oprsz)
{
uint32_t vd_ofs, vj_ofs, vk_ofs;
if (!avail_LSX(ctx)) {
return false;
}
if (!check_vec(ctx, 16)) {
if (!check_vec(ctx, oprsz)) {
return true;
}
@ -3594,13 +3585,9 @@ static bool trans_vandn_v(DisasContext *ctx, arg_vvv *a)
vj_ofs = vec_full_offset(a->vj);
vk_ofs = vec_full_offset(a->vk);
tcg_gen_gvec_andc(MO_64, vd_ofs, vk_ofs, vj_ofs, 16, ctx->vl/8);
tcg_gen_gvec_andc(MO_64, vd_ofs, vk_ofs, vj_ofs, oprsz, ctx->vl / 8);
return true;
}
TRANS(vorn_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_orc)
TRANS(vandi_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_andi)
TRANS(vori_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_ori)
TRANS(vxori_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_xori)
static void gen_vnori(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)
{
@ -3633,7 +3620,26 @@ static void do_vnori_b(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op);
}
TRANS(vand_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_and)
TRANS(vor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_or)
TRANS(vxor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_xor)
TRANS(vnor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_nor)
TRANS(vandn_v, LSX, gen_vandn_v, 16)
TRANS(vorn_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_orc)
TRANS(vandi_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_andi)
TRANS(vori_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_ori)
TRANS(vxori_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_xori)
TRANS(vnori_b, LSX, gvec_vv_i, MO_8, do_vnori_b)
TRANS(xvand_v, LASX, gvec_xxx, MO_64, tcg_gen_gvec_and)
TRANS(xvor_v, LASX, gvec_xxx, MO_64, tcg_gen_gvec_or)
TRANS(xvxor_v, LASX, gvec_xxx, MO_64, tcg_gen_gvec_xor)
TRANS(xvnor_v, LASX, gvec_xxx, MO_64, tcg_gen_gvec_nor)
TRANS(xvandn_v, LASX, gen_vandn_v, 32)
TRANS(xvorn_v, LASX, gvec_xxx, MO_64, tcg_gen_gvec_orc)
TRANS(xvandi_b, LASX, gvec_xx_i, MO_8, tcg_gen_gvec_andi)
TRANS(xvori_b, LASX, gvec_xx_i, MO_8, tcg_gen_gvec_ori)
TRANS(xvxori_b, LASX, gvec_xx_i, MO_8, tcg_gen_gvec_xori)
TRANS(xvnori_b, LASX, gvec_xx_i, MO_8, do_vnori_b)
TRANS(vsll_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_shlv)
TRANS(vsll_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_shlv)

12
target/loongarch/insns.decode
View File

@ -1607,6 +1607,18 @@ xvmsknz_b 0111 01101001 11000 11000 ..... ..... @vv
xvldi 0111 01111110 00 ............. ..... @v_i13
xvand_v 0111 01010010 01100 ..... ..... ..... @vvv
xvor_v 0111 01010010 01101 ..... ..... ..... @vvv
xvxor_v 0111 01010010 01110 ..... ..... ..... @vvv
xvnor_v 0111 01010010 01111 ..... ..... ..... @vvv
xvandn_v 0111 01010010 10000 ..... ..... ..... @vvv
xvorn_v 0111 01010010 10001 ..... ..... ..... @vvv
xvandi_b 0111 01111101 00 ........ ..... ..... @vv_ui8
xvori_b 0111 01111101 01 ........ ..... ..... @vv_ui8
xvxori_b 0111 01111101 10 ........ ..... ..... @vv_ui8
xvnori_b 0111 01111101 11 ........ ..... ..... @vv_ui8
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr

4
target/loongarch/vec_helper.c
View File

@ -941,13 +941,13 @@ void HELPER(vmsknz_b)(void *vd, void *vj, uint32_t desc)
}
}
void HELPER(vnori_b)(void *vd, void *vj, uint64_t imm, uint32_t v)
void HELPER(vnori_b)(void *vd, void *vj, uint64_t imm, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
for (i = 0; i < LSX_LEN/8; i++) {
for (i = 0; i < simd_oprsz(desc); i++) {
Vd->B(i) = ~(Vj->B(i) | (uint8_t)imm);
}
}