net: cadence_gem: Clean up variable names
Cleanup some variable names in preparation for migrating the state struct and type cast macro to a public header. The acronym "GEM" on its own is not specific enough to be used in a more global namespace so preface with "cadence". Fix the capitalisation of "gem" in the state type while touching the typename. Also preface the GEM_MAXREG macro as this will need to migrate to public header. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 8e2b0687b3a7b7a3fde5ba2f3bee6f3b911e84ef.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Crosthwaite
Peter Maydell
parent
bf4cb10966
commit
448f19e231
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@ -141,7 +141,7 @@
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#define GEM_DESCONF6 (0x00000294/4)
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#define GEM_DESCONF7 (0x00000298/4)
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#define GEM_MAXREG (0x00000640/4) /* Last valid GEM address */
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#define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */
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/*****************************************/
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#define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
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@ -350,9 +350,9 @@ static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
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}
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#define TYPE_CADENCE_GEM "cadence_gem"
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#define GEM(obj) OBJECT_CHECK(GemState, (obj), TYPE_CADENCE_GEM)
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#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM)
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typedef struct GemState {
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typedef struct CadenceGEMState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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@ -361,15 +361,15 @@ typedef struct GemState {
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qemu_irq irq;
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/* GEM registers backing store */
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uint32_t regs[GEM_MAXREG];
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uint32_t regs[CADENCE_GEM_MAXREG];
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/* Mask of register bits which are write only */
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uint32_t regs_wo[GEM_MAXREG];
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uint32_t regs_wo[CADENCE_GEM_MAXREG];
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/* Mask of register bits which are read only */
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uint32_t regs_ro[GEM_MAXREG];
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uint32_t regs_ro[CADENCE_GEM_MAXREG];
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/* Mask of register bits which are clear on read */
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uint32_t regs_rtc[GEM_MAXREG];
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uint32_t regs_rtc[CADENCE_GEM_MAXREG];
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/* Mask of register bits which are write 1 to clear */
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uint32_t regs_w1c[GEM_MAXREG];
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uint32_t regs_w1c[CADENCE_GEM_MAXREG];
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/* PHY registers backing store */
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uint16_t phy_regs[32];
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@ -385,7 +385,7 @@ typedef struct GemState {
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unsigned rx_desc[2];
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bool sar_active[4];
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} GemState;
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} CadenceGEMState;
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/* The broadcast MAC address: 0xFFFFFFFFFFFF */
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static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
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@ -395,7 +395,7 @@ static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
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* One time initialization.
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* Set masks to identify which register bits have magical clear properties
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*/
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static void gem_init_register_masks(GemState *s)
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static void gem_init_register_masks(CadenceGEMState *s)
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{
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/* Mask of register bits which are read only */
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memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
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@ -430,7 +430,7 @@ static void gem_init_register_masks(GemState *s)
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* phy_update_link:
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* Make the emulated PHY link state match the QEMU "interface" state.
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*/
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static void phy_update_link(GemState *s)
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static void phy_update_link(CadenceGEMState *s)
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{
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DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
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@ -450,7 +450,7 @@ static void phy_update_link(GemState *s)
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static int gem_can_receive(NetClientState *nc)
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{
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GemState *s;
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CadenceGEMState *s;
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s = qemu_get_nic_opaque(nc);
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@ -483,7 +483,7 @@ static int gem_can_receive(NetClientState *nc)
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* gem_update_int_status:
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* Raise or lower interrupt based on current status.
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*/
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static void gem_update_int_status(GemState *s)
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static void gem_update_int_status(CadenceGEMState *s)
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{
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if (s->regs[GEM_ISR]) {
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DB_PRINT("asserting int. (0x%08x)\n", s->regs[GEM_ISR]);
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@ -495,7 +495,7 @@ static void gem_update_int_status(GemState *s)
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* gem_receive_updatestats:
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* Increment receive statistics.
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*/
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static void gem_receive_updatestats(GemState *s, const uint8_t *packet,
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static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
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unsigned bytes)
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{
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uint64_t octets;
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@ -586,7 +586,7 @@ static unsigned calc_mac_hash(const uint8_t *mac)
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* GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT,
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* GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT
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*/
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static int gem_mac_address_filter(GemState *s, const uint8_t *packet)
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static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
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{
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uint8_t *gem_spaddr;
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int i;
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@ -636,7 +636,7 @@ static int gem_mac_address_filter(GemState *s, const uint8_t *packet)
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return GEM_RX_REJECT;
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}
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static void gem_get_rx_desc(GemState *s)
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static void gem_get_rx_desc(CadenceGEMState *s)
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{
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DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr);
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/* read current descriptor */
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@ -660,7 +660,7 @@ static void gem_get_rx_desc(GemState *s)
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*/
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static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
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{
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GemState *s;
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CadenceGEMState *s;
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unsigned rxbufsize, bytes_to_copy;
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unsigned rxbuf_offset;
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uint8_t rxbuf[2048];
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@ -810,7 +810,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
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* gem_transmit_updatestats:
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* Increment transmit statistics.
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*/
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static void gem_transmit_updatestats(GemState *s, const uint8_t *packet,
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static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
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unsigned bytes)
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{
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uint64_t octets;
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@ -856,7 +856,7 @@ static void gem_transmit_updatestats(GemState *s, const uint8_t *packet,
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* gem_transmit:
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* Fish packets out of the descriptor ring and feed them to QEMU
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*/
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static void gem_transmit(GemState *s)
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static void gem_transmit(CadenceGEMState *s)
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{
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unsigned desc[2];
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hwaddr packet_desc_addr;
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@ -976,7 +976,7 @@ static void gem_transmit(GemState *s)
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}
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}
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static void gem_phy_reset(GemState *s)
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static void gem_phy_reset(CadenceGEMState *s)
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{
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memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
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s->phy_regs[PHY_REG_CONTROL] = 0x1140;
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@ -1004,7 +1004,7 @@ static void gem_phy_reset(GemState *s)
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static void gem_reset(DeviceState *d)
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{
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int i;
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GemState *s = GEM(d);
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CadenceGEMState *s = CADENCE_GEM(d);
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DB_PRINT("\n");
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@ -1032,13 +1032,13 @@ static void gem_reset(DeviceState *d)
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gem_update_int_status(s);
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}
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static uint16_t gem_phy_read(GemState *s, unsigned reg_num)
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static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num)
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{
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DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]);
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return s->phy_regs[reg_num];
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}
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static void gem_phy_write(GemState *s, unsigned reg_num, uint16_t val)
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static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
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{
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DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val);
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@ -1072,10 +1072,10 @@ static void gem_phy_write(GemState *s, unsigned reg_num, uint16_t val)
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*/
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static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
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{
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GemState *s;
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CadenceGEMState *s;
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uint32_t retval;
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s = (GemState *)opaque;
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s = (CadenceGEMState *)opaque;
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offset >>= 2;
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retval = s->regs[offset];
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@ -1120,7 +1120,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
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static void gem_write(void *opaque, hwaddr offset, uint64_t val,
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unsigned size)
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{
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GemState *s = (GemState *)opaque;
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CadenceGEMState *s = (CadenceGEMState *)opaque;
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uint32_t readonly;
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DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
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@ -1226,7 +1226,7 @@ static NetClientInfo net_gem_info = {
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static int gem_init(SysBusDevice *sbd)
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{
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DeviceState *dev = DEVICE(sbd);
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GemState *s = GEM(dev);
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CadenceGEMState *s = CADENCE_GEM(dev);
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DB_PRINT("\n");
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@ -1248,18 +1248,18 @@ static const VMStateDescription vmstate_cadence_gem = {
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, GemState, GEM_MAXREG),
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VMSTATE_UINT16_ARRAY(phy_regs, GemState, 32),
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VMSTATE_UINT8(phy_loop, GemState),
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VMSTATE_UINT32(rx_desc_addr, GemState),
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VMSTATE_UINT32(tx_desc_addr, GemState),
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VMSTATE_BOOL_ARRAY(sar_active, GemState, 4),
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VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
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VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32),
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VMSTATE_UINT8(phy_loop, CadenceGEMState),
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VMSTATE_UINT32(rx_desc_addr, CadenceGEMState),
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VMSTATE_UINT32(tx_desc_addr, CadenceGEMState),
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VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
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VMSTATE_END_OF_LIST(),
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}
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};
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static Property gem_properties[] = {
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DEFINE_NIC_PROPERTIES(GemState, conf),
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DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -1277,7 +1277,7 @@ static void gem_class_init(ObjectClass *klass, void *data)
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static const TypeInfo gem_info = {
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.name = TYPE_CADENCE_GEM,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(GemState),
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.instance_size = sizeof(CadenceGEMState),
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.class_init = gem_class_init,
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};
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