target/arm: Do not use gen_mte_checkN in trans_STGP
STGP writes to tag memory, it does not check it. This happened to work because we wrote tag memory first so that the check always succeeded. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230901203103.136408-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3020,37 +3020,17 @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a)
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tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
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}
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if (!s->ata) {
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/*
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* TODO: We could rely on the stores below, at least for
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* system mode, if we arrange to add MO_ALIGN_16.
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*/
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gen_helper_stg_stub(cpu_env, dirty_addr);
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} else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
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gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr);
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} else {
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gen_helper_stg(cpu_env, dirty_addr, dirty_addr);
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}
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mop = finalize_memop(s, MO_64);
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clean_addr = gen_mte_checkN(s, dirty_addr, true, false, 2 << MO_64, mop);
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clean_addr = clean_data_tbi(s, dirty_addr);
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tcg_rt = cpu_reg(s, a->rt);
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tcg_rt2 = cpu_reg(s, a->rt2);
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/*
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* STGP is defined as two 8-byte memory operations and one tag operation.
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* We implement it as one single 16-byte memory operation for convenience.
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* Rebuild mop as for STP.
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* TODO: The atomicity with LSE2 is stronger than required.
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* Need a form of MO_ATOM_WITHIN16_PAIR that never requires
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* 16-byte atomicity.
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* STGP is defined as two 8-byte memory operations, aligned to TAG_GRANULE,
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* and one tag operation. We implement it as one single aligned 16-byte
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* memory operation for convenience. Note that the alignment ensures
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* MO_ATOM_IFALIGN_PAIR produces 8-byte atomicity for the memory store.
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*/
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mop = MO_128;
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if (s->align_mem) {
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mop |= MO_ALIGN_8;
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}
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mop = finalize_memop_pair(s, mop);
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mop = finalize_memop_atom(s, MO_128 | MO_ALIGN, MO_ATOM_IFALIGN_PAIR);
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tmp = tcg_temp_new_i128();
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if (s->be_data == MO_LE) {
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@ -3060,6 +3040,15 @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a)
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}
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tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop);
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/* Perform the tag store, if tag access enabled. */
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if (s->ata) {
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if (tb_cflags(s->base.tb) & CF_PARALLEL) {
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gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr);
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} else {
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gen_helper_stg(cpu_env, dirty_addr, dirty_addr);
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}
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}
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op_addr_ldstpair_post(s, a, dirty_addr, offset);
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return true;
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}
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