tcg/i386: Split subroutines out of tcg_expand_vec_op
This routine was becoming too large. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
dd0a0fcdd8
commit
44f1441dbe
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@ -3079,253 +3079,258 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
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}
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}
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static void expand_vec_shi(TCGType type, unsigned vece, bool shr,
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TCGv_vec v0, TCGv_vec v1, TCGArg imm)
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{
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TCGv_vec t1, t2;
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tcg_debug_assert(vece == MO_8);
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t1 = tcg_temp_new_vec(type);
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t2 = tcg_temp_new_vec(type);
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/* Unpack to W, shift, and repack. Tricky bits:
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(1) Use punpck*bw x,x to produce DDCCBBAA,
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i.e. duplicate in other half of the 16-bit lane.
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(2) For right-shift, add 8 so that the high half of
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the lane becomes zero. For left-shift, we must
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shift up and down again.
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(3) Step 2 leaves high half zero such that PACKUSWB
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(pack with unsigned saturation) does not modify
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the quantity. */
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vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
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tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
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vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
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tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
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if (shr) {
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tcg_gen_shri_vec(MO_16, t1, t1, imm + 8);
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tcg_gen_shri_vec(MO_16, t2, t2, imm + 8);
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} else {
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tcg_gen_shli_vec(MO_16, t1, t1, imm + 8);
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tcg_gen_shli_vec(MO_16, t2, t2, imm + 8);
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tcg_gen_shri_vec(MO_16, t1, t1, 8);
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tcg_gen_shri_vec(MO_16, t2, t2, 8);
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}
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vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
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tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));
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tcg_temp_free_vec(t1);
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tcg_temp_free_vec(t2);
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}
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static void expand_vec_sari(TCGType type, unsigned vece,
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TCGv_vec v0, TCGv_vec v1, TCGArg imm)
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{
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TCGv_vec t1, t2;
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switch (vece) {
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case MO_8:
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/* Unpack to W, shift, and repack, as in expand_vec_shi. */
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t1 = tcg_temp_new_vec(type);
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t2 = tcg_temp_new_vec(type);
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vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
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tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
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vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
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tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
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tcg_gen_sari_vec(MO_16, t1, t1, imm + 8);
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tcg_gen_sari_vec(MO_16, t2, t2, imm + 8);
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vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8,
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tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));
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tcg_temp_free_vec(t1);
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tcg_temp_free_vec(t2);
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break;
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case MO_64:
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if (imm <= 32) {
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/* We can emulate a small sign extend by performing an arithmetic
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* 32-bit shift and overwriting the high half of a 64-bit logical
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* shift (note that the ISA says shift of 32 is valid).
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*/
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t1 = tcg_temp_new_vec(type);
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tcg_gen_sari_vec(MO_32, t1, v1, imm);
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tcg_gen_shri_vec(MO_64, v0, v1, imm);
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vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
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tcgv_vec_arg(v0), tcgv_vec_arg(v0),
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tcgv_vec_arg(t1), 0xaa);
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tcg_temp_free_vec(t1);
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} else {
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/* Otherwise we will need to use a compare vs 0 to produce
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* the sign-extend, shift and merge.
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*/
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t1 = tcg_const_zeros_vec(type);
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tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1);
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tcg_gen_shri_vec(MO_64, v0, v1, imm);
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tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm);
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tcg_gen_or_vec(MO_64, v0, v0, t1);
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tcg_temp_free_vec(t1);
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}
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void expand_vec_mul(TCGType type, unsigned vece,
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TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)
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{
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TCGv_vec t1, t2, t3, t4;
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tcg_debug_assert(vece == MO_8);
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/*
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* Unpack v1 bytes to words, 0 | x.
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* Unpack v2 bytes to words, y | 0.
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* This leaves the 8-bit result, x * y, with 8 bits of right padding.
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* Shift logical right by 8 bits to clear the high 8 bytes before
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* using an unsigned saturated pack.
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*
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* The difference between the V64, V128 and V256 cases is merely how
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* we distribute the expansion between temporaries.
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*/
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switch (type) {
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case TCG_TYPE_V64:
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t1 = tcg_temp_new_vec(TCG_TYPE_V128);
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t2 = tcg_temp_new_vec(TCG_TYPE_V128);
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tcg_gen_dup16i_vec(t2, 0);
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vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
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tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2));
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vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
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tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2));
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tcg_gen_mul_vec(MO_16, t1, t1, t2);
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tcg_gen_shri_vec(MO_16, t1, t1, 8);
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vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
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tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1));
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tcg_temp_free_vec(t1);
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tcg_temp_free_vec(t2);
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break;
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case TCG_TYPE_V128:
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case TCG_TYPE_V256:
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t1 = tcg_temp_new_vec(type);
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t2 = tcg_temp_new_vec(type);
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t3 = tcg_temp_new_vec(type);
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t4 = tcg_temp_new_vec(type);
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tcg_gen_dup16i_vec(t4, 0);
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vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
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tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4));
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vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
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tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2));
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vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
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tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4));
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vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
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tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2));
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tcg_gen_mul_vec(MO_16, t1, t1, t2);
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tcg_gen_mul_vec(MO_16, t3, t3, t4);
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tcg_gen_shri_vec(MO_16, t1, t1, 8);
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tcg_gen_shri_vec(MO_16, t3, t3, 8);
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vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
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tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3));
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tcg_temp_free_vec(t1);
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tcg_temp_free_vec(t2);
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tcg_temp_free_vec(t3);
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tcg_temp_free_vec(t4);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
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TCGv_vec v1, TCGv_vec v2, TCGCond cond)
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{
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enum {
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NEED_SWAP = 1,
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NEED_INV = 2,
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NEED_BIAS = 4
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};
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static const uint8_t fixups[16] = {
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[0 ... 15] = -1,
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[TCG_COND_EQ] = 0,
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[TCG_COND_NE] = NEED_INV,
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[TCG_COND_GT] = 0,
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[TCG_COND_LT] = NEED_SWAP,
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[TCG_COND_LE] = NEED_INV,
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[TCG_COND_GE] = NEED_SWAP | NEED_INV,
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[TCG_COND_GTU] = NEED_BIAS,
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[TCG_COND_LTU] = NEED_BIAS | NEED_SWAP,
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[TCG_COND_LEU] = NEED_BIAS | NEED_INV,
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[TCG_COND_GEU] = NEED_BIAS | NEED_SWAP | NEED_INV,
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};
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TCGv_vec t1, t2;
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uint8_t fixup;
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fixup = fixups[cond & 15];
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tcg_debug_assert(fixup != 0xff);
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if (fixup & NEED_INV) {
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cond = tcg_invert_cond(cond);
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}
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if (fixup & NEED_SWAP) {
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t1 = v1, v1 = v2, v2 = t1;
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cond = tcg_swap_cond(cond);
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}
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t1 = t2 = NULL;
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if (fixup & NEED_BIAS) {
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t1 = tcg_temp_new_vec(type);
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t2 = tcg_temp_new_vec(type);
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tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1));
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tcg_gen_sub_vec(vece, t1, v1, t2);
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tcg_gen_sub_vec(vece, t2, v2, t2);
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v1 = t1;
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v2 = t2;
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cond = tcg_signed_cond(cond);
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}
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tcg_debug_assert(cond == TCG_COND_EQ || cond == TCG_COND_GT);
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/* Expand directly; do not recurse. */
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vec_gen_4(INDEX_op_cmp_vec, type, vece,
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tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
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if (t1) {
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tcg_temp_free_vec(t1);
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if (t2) {
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tcg_temp_free_vec(t2);
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}
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}
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if (fixup & NEED_INV) {
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tcg_gen_not_vec(vece, v0, v0);
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}
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}
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void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
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TCGArg a0, ...)
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{
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va_list va;
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TCGArg a1, a2;
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TCGv_vec v0, t1, t2, t3, t4;
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TCGArg a2;
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TCGv_vec v0, v1, v2;
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va_start(va, a0);
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v0 = temp_tcgv_vec(arg_temp(a0));
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v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
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a2 = va_arg(va, TCGArg);
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switch (opc) {
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case INDEX_op_shli_vec:
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case INDEX_op_shri_vec:
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tcg_debug_assert(vece == MO_8);
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a1 = va_arg(va, TCGArg);
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a2 = va_arg(va, TCGArg);
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/* Unpack to W, shift, and repack. Tricky bits:
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(1) Use punpck*bw x,x to produce DDCCBBAA,
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i.e. duplicate in other half of the 16-bit lane.
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(2) For right-shift, add 8 so that the high half of
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the lane becomes zero. For left-shift, we must
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shift up and down again.
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(3) Step 2 leaves high half zero such that PACKUSWB
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(pack with unsigned saturation) does not modify
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the quantity. */
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t1 = tcg_temp_new_vec(type);
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t2 = tcg_temp_new_vec(type);
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vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
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tcgv_vec_arg(t1), a1, a1);
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vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
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tcgv_vec_arg(t2), a1, a1);
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if (opc == INDEX_op_shri_vec) {
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vec_gen_3(INDEX_op_shri_vec, type, MO_16,
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tcgv_vec_arg(t1), tcgv_vec_arg(t1), a2 + 8);
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vec_gen_3(INDEX_op_shri_vec, type, MO_16,
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tcgv_vec_arg(t2), tcgv_vec_arg(t2), a2 + 8);
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} else {
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vec_gen_3(INDEX_op_shli_vec, type, MO_16,
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tcgv_vec_arg(t1), tcgv_vec_arg(t1), a2 + 8);
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vec_gen_3(INDEX_op_shli_vec, type, MO_16,
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tcgv_vec_arg(t2), tcgv_vec_arg(t2), a2 + 8);
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vec_gen_3(INDEX_op_shri_vec, type, MO_16,
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tcgv_vec_arg(t1), tcgv_vec_arg(t1), 8);
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vec_gen_3(INDEX_op_shri_vec, type, MO_16,
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tcgv_vec_arg(t2), tcgv_vec_arg(t2), 8);
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}
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vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
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a0, tcgv_vec_arg(t1), tcgv_vec_arg(t2));
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tcg_temp_free_vec(t1);
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tcg_temp_free_vec(t2);
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expand_vec_shi(type, vece, opc == INDEX_op_shri_vec, v0, v1, a2);
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break;
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case INDEX_op_sari_vec:
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a1 = va_arg(va, TCGArg);
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a2 = va_arg(va, TCGArg);
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if (vece == MO_8) {
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/* Unpack to W, shift, and repack, as above. */
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t1 = tcg_temp_new_vec(type);
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t2 = tcg_temp_new_vec(type);
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vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
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tcgv_vec_arg(t1), a1, a1);
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vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
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tcgv_vec_arg(t2), a1, a1);
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vec_gen_3(INDEX_op_sari_vec, type, MO_16,
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tcgv_vec_arg(t1), tcgv_vec_arg(t1), a2 + 8);
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vec_gen_3(INDEX_op_sari_vec, type, MO_16,
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tcgv_vec_arg(t2), tcgv_vec_arg(t2), a2 + 8);
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vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8,
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a0, tcgv_vec_arg(t1), tcgv_vec_arg(t2));
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tcg_temp_free_vec(t1);
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tcg_temp_free_vec(t2);
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break;
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}
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tcg_debug_assert(vece == MO_64);
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/* MO_64: If the shift is <= 32, we can emulate the sign extend by
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performing an arithmetic 32-bit shift and overwriting the high
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half of the result (note that the ISA says shift of 32 is valid). */
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if (a2 <= 32) {
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t1 = tcg_temp_new_vec(type);
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vec_gen_3(INDEX_op_sari_vec, type, MO_32, tcgv_vec_arg(t1), a1, a2);
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vec_gen_3(INDEX_op_shri_vec, type, MO_64, a0, a1, a2);
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vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
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a0, a0, tcgv_vec_arg(t1), 0xaa);
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tcg_temp_free_vec(t1);
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break;
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}
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/* Otherwise we will need to use a compare vs 0 to produce the
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sign-extend, shift and merge. */
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t1 = tcg_temp_new_vec(type);
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t2 = tcg_const_zeros_vec(type);
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vec_gen_4(INDEX_op_cmp_vec, type, MO_64,
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tcgv_vec_arg(t1), tcgv_vec_arg(t2), a1, TCG_COND_GT);
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tcg_temp_free_vec(t2);
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vec_gen_3(INDEX_op_shri_vec, type, MO_64, a0, a1, a2);
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vec_gen_3(INDEX_op_shli_vec, type, MO_64,
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tcgv_vec_arg(t1), tcgv_vec_arg(t1), 64 - a2);
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vec_gen_3(INDEX_op_or_vec, type, MO_64, a0, a0, tcgv_vec_arg(t1));
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tcg_temp_free_vec(t1);
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expand_vec_sari(type, vece, v0, v1, a2);
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break;
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case INDEX_op_mul_vec:
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tcg_debug_assert(vece == MO_8);
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a1 = va_arg(va, TCGArg);
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a2 = va_arg(va, TCGArg);
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switch (type) {
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case TCG_TYPE_V64:
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t1 = tcg_temp_new_vec(TCG_TYPE_V128);
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t2 = tcg_temp_new_vec(TCG_TYPE_V128);
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tcg_gen_dup16i_vec(t2, 0);
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vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
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tcgv_vec_arg(t1), a1, tcgv_vec_arg(t2));
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vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
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tcgv_vec_arg(t2), tcgv_vec_arg(t2), a2);
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tcg_gen_mul_vec(MO_16, t1, t1, t2);
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tcg_gen_shri_vec(MO_16, t1, t1, 8);
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vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
|
||||
a0, tcgv_vec_arg(t1), tcgv_vec_arg(t1));
|
||||
tcg_temp_free_vec(t1);
|
||||
tcg_temp_free_vec(t2);
|
||||
break;
|
||||
|
||||
case TCG_TYPE_V128:
|
||||
t1 = tcg_temp_new_vec(TCG_TYPE_V128);
|
||||
t2 = tcg_temp_new_vec(TCG_TYPE_V128);
|
||||
t3 = tcg_temp_new_vec(TCG_TYPE_V128);
|
||||
t4 = tcg_temp_new_vec(TCG_TYPE_V128);
|
||||
tcg_gen_dup16i_vec(t4, 0);
|
||||
vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
|
||||
tcgv_vec_arg(t1), a1, tcgv_vec_arg(t4));
|
||||
vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
|
||||
tcgv_vec_arg(t2), tcgv_vec_arg(t4), a2);
|
||||
vec_gen_3(INDEX_op_x86_punpckh_vec, TCG_TYPE_V128, MO_8,
|
||||
tcgv_vec_arg(t3), a1, tcgv_vec_arg(t4));
|
||||
vec_gen_3(INDEX_op_x86_punpckh_vec, TCG_TYPE_V128, MO_8,
|
||||
tcgv_vec_arg(t4), tcgv_vec_arg(t4), a2);
|
||||
tcg_gen_mul_vec(MO_16, t1, t1, t2);
|
||||
tcg_gen_mul_vec(MO_16, t3, t3, t4);
|
||||
tcg_gen_shri_vec(MO_16, t1, t1, 8);
|
||||
tcg_gen_shri_vec(MO_16, t3, t3, 8);
|
||||
vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
|
||||
a0, tcgv_vec_arg(t1), tcgv_vec_arg(t3));
|
||||
tcg_temp_free_vec(t1);
|
||||
tcg_temp_free_vec(t2);
|
||||
tcg_temp_free_vec(t3);
|
||||
tcg_temp_free_vec(t4);
|
||||
break;
|
||||
|
||||
case TCG_TYPE_V256:
|
||||
t1 = tcg_temp_new_vec(TCG_TYPE_V256);
|
||||
t2 = tcg_temp_new_vec(TCG_TYPE_V256);
|
||||
t3 = tcg_temp_new_vec(TCG_TYPE_V256);
|
||||
t4 = tcg_temp_new_vec(TCG_TYPE_V256);
|
||||
tcg_gen_dup16i_vec(t4, 0);
|
||||
/* a1: A[0-7] ... D[0-7]; a2: W[0-7] ... Z[0-7]
|
||||
t1: extends of B[0-7], D[0-7]
|
||||
t2: extends of X[0-7], Z[0-7]
|
||||
t3: extends of A[0-7], C[0-7]
|
||||
t4: extends of W[0-7], Y[0-7]. */
|
||||
vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V256, MO_8,
|
||||
tcgv_vec_arg(t1), a1, tcgv_vec_arg(t4));
|
||||
vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V256, MO_8,
|
||||
tcgv_vec_arg(t2), tcgv_vec_arg(t4), a2);
|
||||
vec_gen_3(INDEX_op_x86_punpckh_vec, TCG_TYPE_V256, MO_8,
|
||||
tcgv_vec_arg(t3), a1, tcgv_vec_arg(t4));
|
||||
vec_gen_3(INDEX_op_x86_punpckh_vec, TCG_TYPE_V256, MO_8,
|
||||
tcgv_vec_arg(t4), tcgv_vec_arg(t4), a2);
|
||||
/* t1: BX DZ; t2: AW CY. */
|
||||
tcg_gen_mul_vec(MO_16, t1, t1, t2);
|
||||
tcg_gen_mul_vec(MO_16, t3, t3, t4);
|
||||
tcg_gen_shri_vec(MO_16, t1, t1, 8);
|
||||
tcg_gen_shri_vec(MO_16, t3, t3, 8);
|
||||
/* a0: AW BX CY DZ. */
|
||||
vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V256, MO_8,
|
||||
a0, tcgv_vec_arg(t1), tcgv_vec_arg(t3));
|
||||
tcg_temp_free_vec(t1);
|
||||
tcg_temp_free_vec(t2);
|
||||
tcg_temp_free_vec(t3);
|
||||
tcg_temp_free_vec(t4);
|
||||
break;
|
||||
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
v2 = temp_tcgv_vec(arg_temp(a2));
|
||||
expand_vec_mul(type, vece, v0, v1, v2);
|
||||
break;
|
||||
|
||||
case INDEX_op_cmp_vec:
|
||||
{
|
||||
enum {
|
||||
NEED_SWAP = 1,
|
||||
NEED_INV = 2,
|
||||
NEED_BIAS = 4
|
||||
};
|
||||
static const uint8_t fixups[16] = {
|
||||
[0 ... 15] = -1,
|
||||
[TCG_COND_EQ] = 0,
|
||||
[TCG_COND_NE] = NEED_INV,
|
||||
[TCG_COND_GT] = 0,
|
||||
[TCG_COND_LT] = NEED_SWAP,
|
||||
[TCG_COND_LE] = NEED_INV,
|
||||
[TCG_COND_GE] = NEED_SWAP | NEED_INV,
|
||||
[TCG_COND_GTU] = NEED_BIAS,
|
||||
[TCG_COND_LTU] = NEED_BIAS | NEED_SWAP,
|
||||
[TCG_COND_LEU] = NEED_BIAS | NEED_INV,
|
||||
[TCG_COND_GEU] = NEED_BIAS | NEED_SWAP | NEED_INV,
|
||||
};
|
||||
|
||||
TCGCond cond;
|
||||
uint8_t fixup;
|
||||
|
||||
a1 = va_arg(va, TCGArg);
|
||||
a2 = va_arg(va, TCGArg);
|
||||
cond = va_arg(va, TCGArg);
|
||||
fixup = fixups[cond & 15];
|
||||
tcg_debug_assert(fixup != 0xff);
|
||||
|
||||
if (fixup & NEED_INV) {
|
||||
cond = tcg_invert_cond(cond);
|
||||
}
|
||||
if (fixup & NEED_SWAP) {
|
||||
TCGArg t;
|
||||
t = a1, a1 = a2, a2 = t;
|
||||
cond = tcg_swap_cond(cond);
|
||||
}
|
||||
|
||||
t1 = t2 = NULL;
|
||||
if (fixup & NEED_BIAS) {
|
||||
t1 = tcg_temp_new_vec(type);
|
||||
t2 = tcg_temp_new_vec(type);
|
||||
tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1));
|
||||
tcg_gen_sub_vec(vece, t1, temp_tcgv_vec(arg_temp(a1)), t2);
|
||||
tcg_gen_sub_vec(vece, t2, temp_tcgv_vec(arg_temp(a2)), t2);
|
||||
a1 = tcgv_vec_arg(t1);
|
||||
a2 = tcgv_vec_arg(t2);
|
||||
cond = tcg_signed_cond(cond);
|
||||
}
|
||||
|
||||
tcg_debug_assert(cond == TCG_COND_EQ || cond == TCG_COND_GT);
|
||||
vec_gen_4(INDEX_op_cmp_vec, type, vece, a0, a1, a2, cond);
|
||||
|
||||
if (fixup & NEED_BIAS) {
|
||||
tcg_temp_free_vec(t1);
|
||||
tcg_temp_free_vec(t2);
|
||||
}
|
||||
if (fixup & NEED_INV) {
|
||||
tcg_gen_not_vec(vece, v0, v0);
|
||||
}
|
||||
}
|
||||
v2 = temp_tcgv_vec(arg_temp(a2));
|
||||
expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
|||
Loading…
Reference in New Issue