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target/mips: Enable LBX/LWX/* instructions for Octeon 

This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Pavel Dovgalyuk 2022-11-01 08:29:44 +03:00 committed by Philippe Mathieu-Daudé
parent 0e8b3010af
commit 4525ea7e0c
1 changed files with 8 additions and 4 deletions
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8
target/mips/tcg/translate.c
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@ -12173,12 +12173,16 @@ enum {
#include "nanomips_translate.c.inc"
/* MIPSDSP functions. */
static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc,
/* Indexed load is not for DSP only */
static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
int rd, int base, int offset)
{
TCGv t0;
if (!(ctx->insn_flags & INSN_OCTEON)) {
check_dsp(ctx);
}
t0 = tcg_temp_new();
if (base == 0) {
@ -14523,7 +14527,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_LBUX:
case OPC_LHX:
case OPC_LWX:
gen_mipsdsp_ld(ctx, op2, rd, rs, rt);
gen_mips_lx(ctx, op2, rd, rs, rt);
break;
default: /* Invalid */
MIPS_INVAL("MASK LX");