pci: SLT must be RO
current code sets PCI_SEC_LATENCY_TIMER to RW, but for pcie to pcie bridges it must be RO 0 according to pci express spec which says: This register does not apply to PCI Express. It must be read-only and hardwired to 00h. For PCI Express to PCI/PCI-X Bridges, refer to the [PCIe-to-PCI-PCI-X-Bridge] for requirements for this register. also, fix typo in comment where it's made writeable - this typo is likely what prevented us noticing we violate this requirement in the 1st place. Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-Id: <de9d05366a70172e1789d10591dbe59e39c3849c.1693432039.git.mst@redhat.com> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -32,6 +32,7 @@
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#include "qemu/error-report.h"
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#include "sysemu/qtest.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/mem/nvdimm.h"
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#include "migration/global_state.h"
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#include "migration/vmstate.h"
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@ -40,7 +41,9 @@
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#include "hw/virtio/virtio-pci.h"
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#include "hw/virtio/virtio-net.h"
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GlobalProperty hw_compat_8_1[] = {};
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GlobalProperty hw_compat_8_1[] = {
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{ TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" },
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};
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const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1);
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GlobalProperty hw_compat_8_0[] = {
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@ -893,7 +893,7 @@ static void pci_init_w1cmask(PCIDevice *dev)
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static void pci_init_mask_bridge(PCIDevice *d)
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{
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/* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
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PCI_SEC_LETENCY_TIMER */
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PCI_SEC_LATENCY_TIMER */
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memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
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/* base and limit */
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@ -38,6 +38,7 @@
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#include "qapi/error.h"
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#include "hw/acpi/acpi_aml_interface.h"
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#include "hw/acpi/pci.h"
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#include "hw/qdev-properties.h"
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/* PCI bridge subsystem vendor ID helper functions */
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#define PCI_SSVID_SIZEOF 8
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@ -385,6 +386,11 @@ void pci_bridge_initfn(PCIDevice *dev, const char *typename)
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pci_bridge_region_init(br);
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QLIST_INIT(&sec_bus->child);
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QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
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/* For express secondary buses, secondary latency timer is RO 0 */
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if (pci_bus_is_express(sec_bus) && !br->pcie_writeable_slt_bug) {
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dev->wmask[PCI_SEC_LATENCY_TIMER] = 0;
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}
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}
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/* default qdev clean up function for PCI-to-PCI bridge */
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@ -466,10 +472,18 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
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return 0;
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}
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static Property pci_bridge_properties[] = {
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DEFINE_PROP_BOOL("x-pci-express-writeable-slt-bug", PCIBridge,
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pcie_writeable_slt_bug, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pci_bridge_class_init(ObjectClass *klass, void *data)
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{
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AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
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DeviceClass *k = DEVICE_CLASS(klass);
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device_class_set_props(k, pci_bridge_properties);
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adevc->build_dev_aml = build_pci_bridge_aml;
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}
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@ -77,6 +77,9 @@ struct PCIBridge {
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pci_map_irq_fn map_irq;
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const char *bus_name;
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/* SLT is RO for PCIE to PCIE bridges, but old QEMU versions had it RW */
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bool pcie_writeable_slt_bug;
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};
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#define PCI_BRIDGE_DEV_PROP_CHASSIS_NR "chassis_nr"
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