target/riscv: actual functions to realize crs 128-bit insns
The csrs are accessed through function pointers: we add 128-bit read operations in the table for three csrs (writes fallback to the 64-bit version as the upper 64-bit information is handled elsewhere): - misa, as mxl is needed for proper operation, - mstatus and sstatus, to return sd In addition, we also add read and write accesses to the machine and supervisor scratch registers. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-19-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frédéric Pétrot
Alistair Francis
parent
7934fdeee7
commit
457c360f9c
@ -505,12 +505,19 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
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Int128 *ret_value,
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Int128 new_value, Int128 write_mask);
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typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
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Int128 *ret_value);
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typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
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Int128 new_value);
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typedef struct {
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const char *name;
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riscv_csr_predicate_fn predicate;
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riscv_csr_read_fn read;
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riscv_csr_write_fn write;
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riscv_csr_op_fn op;
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riscv_csr_read128_fn read128;
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riscv_csr_write128_fn write128;
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} riscv_csr_operations;
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/* CSR function table constants */
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@ -401,6 +401,7 @@
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#define MSTATUS32_SD 0x80000000
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#define MSTATUS64_SD 0x8000000000000000ULL
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#define MSTATUSH128_SD 0x8000000000000000ULL
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#define MISA32_MXL 0xC0000000
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#define MISA64_MXL 0xC000000000000000ULL
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@ -423,6 +424,8 @@ typedef enum {
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#define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */
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#define SSTATUS_MXR 0x00080000
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#define SSTATUS64_UXL 0x0000000300000000ULL
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#define SSTATUS32_SD 0x80000000
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#define SSTATUS64_SD 0x8000000000000000ULL
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@ -481,7 +481,7 @@ static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
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(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
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static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
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SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
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SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
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SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL;
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static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
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static const target_ulong hip_writable_mask = MIP_VSSIP;
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static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
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@ -527,6 +527,8 @@ static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
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return status | MSTATUS32_SD;
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case MXL_RV64:
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return status | MSTATUS64_SD;
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case MXL_RV128:
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return MSTATUSH128_SD;
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default:
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g_assert_not_reached();
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}
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@ -576,10 +578,11 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
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mstatus = (mstatus & ~mask) | (val & mask);
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if (riscv_cpu_mxl(env) == MXL_RV64) {
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RISCVMXL xl = riscv_cpu_mxl(env);
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if (xl > MXL_RV32) {
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/* SXL and UXL fields are for now read only */
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mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
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mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
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mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
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mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
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}
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env->mstatus = mstatus;
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@ -608,6 +611,20 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
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Int128 *val)
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{
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*val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
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Int128 *val)
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{
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*val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62);
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_misa(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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@ -765,6 +782,21 @@ static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
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}
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/* Machine Trap Handling */
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static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
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Int128 *val)
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{
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*val = int128_make128(env->mscratch, env->mscratchh);
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
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Int128 val)
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{
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env->mscratch = int128_getlo(val);
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env->mscratchh = int128_gethi(val);
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_mscratch(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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@ -844,6 +876,16 @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
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}
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/* Supervisor Trap Setup */
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static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
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Int128 *val)
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{
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uint64_t mask = sstatus_v1_10_mask;
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uint64_t sstatus = env->mstatus & mask;
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*val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_sstatus(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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@ -937,6 +979,21 @@ static RISCVException write_scounteren(CPURISCVState *env, int csrno,
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}
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/* Supervisor Trap Handling */
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static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno,
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Int128 *val)
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{
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*val = int128_make128(env->sscratch, env->sscratchh);
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno,
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Int128 val)
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{
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env->sscratch = int128_getlo(val);
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env->sscratchh = int128_gethi(val);
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_sscratch(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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@ -1737,16 +1794,13 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
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* csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value);
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*/
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RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
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target_ulong *ret_value,
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target_ulong new_value, target_ulong write_mask)
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static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
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int csrno,
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bool write_mask,
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RISCVCPU *cpu)
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{
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RISCVException ret;
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target_ulong old_value;
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RISCVCPU *cpu = env_archcpu(env);
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int read_only = get_field(csrno, 0xC00) == 3;
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/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
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int read_only = get_field(csrno, 0xC00) == 3;
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#if !defined(CONFIG_USER_ONLY)
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int effective_priv = env->priv;
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@ -1778,10 +1832,17 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
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if (!csr_ops[csrno].predicate) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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ret = csr_ops[csrno].predicate(env, csrno);
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if (ret != RISCV_EXCP_NONE) {
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return ret;
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}
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return csr_ops[csrno].predicate(env, csrno);
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}
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static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
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target_ulong *ret_value,
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target_ulong new_value,
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target_ulong write_mask)
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{
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RISCVException ret;
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target_ulong old_value;
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/* execute combined read/write operation if it exists */
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if (csr_ops[csrno].op) {
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@ -1817,20 +1878,89 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
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return RISCV_EXCP_NONE;
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}
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RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
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Int128 *ret_value,
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Int128 new_value, Int128 write_mask)
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RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
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target_ulong *ret_value,
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target_ulong new_value, target_ulong write_mask)
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{
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/* fall back to 64-bit version for now */
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target_ulong ret_64;
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RISCVException ret = riscv_csrrw(env, csrno, &ret_64,
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int128_getlo(new_value),
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int128_getlo(write_mask));
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RISCVCPU *cpu = env_archcpu(env);
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if (ret_value) {
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*ret_value = int128_make64(ret_64);
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RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
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if (ret != RISCV_EXCP_NONE) {
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return ret;
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}
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return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
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}
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static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
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Int128 *ret_value,
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Int128 new_value,
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Int128 write_mask)
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{
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RISCVException ret;
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Int128 old_value;
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/* read old value */
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ret = csr_ops[csrno].read128(env, csrno, &old_value);
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if (ret != RISCV_EXCP_NONE) {
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return ret;
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}
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/* write value if writable and write mask set, otherwise drop writes */
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if (int128_nz(write_mask)) {
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new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
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int128_and(new_value, write_mask));
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if (csr_ops[csrno].write128) {
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ret = csr_ops[csrno].write128(env, csrno, new_value);
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if (ret != RISCV_EXCP_NONE) {
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return ret;
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}
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} else if (csr_ops[csrno].write) {
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/* avoids having to write wrappers for all registers */
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ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value));
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if (ret != RISCV_EXCP_NONE) {
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return ret;
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}
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}
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}
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/* return old value */
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if (ret_value) {
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*ret_value = old_value;
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}
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return RISCV_EXCP_NONE;
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}
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RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
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Int128 *ret_value,
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Int128 new_value, Int128 write_mask)
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{
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RISCVException ret;
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RISCVCPU *cpu = env_archcpu(env);
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ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
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if (ret != RISCV_EXCP_NONE) {
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return ret;
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}
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if (csr_ops[csrno].read128) {
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return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask);
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}
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/*
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* Fall back to 64-bit version for now, if the 128-bit alternative isn't
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* at all defined.
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* Note, some CSRs don't need to extend to MXLEN (64 upper bits non
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* significant), for those, this fallback is correctly handling the accesses
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*/
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target_ulong old_value;
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ret = riscv_csrrw_do64(env, csrno, &old_value,
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int128_getlo(new_value),
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int128_getlo(write_mask));
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if (ret == RISCV_EXCP_NONE && ret_value) {
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*ret_value = int128_make64(old_value);
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}
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return ret;
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}
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@ -1895,8 +2025,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_MHARTID] = { "mhartid", any, read_mhartid },
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/* Machine Trap Setup */
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[CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus },
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[CSR_MISA] = { "misa", any, read_misa, write_misa },
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[CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL,
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read_mstatus_i128 },
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[CSR_MISA] = { "misa", any, read_misa, write_misa, NULL,
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read_misa_i128 },
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[CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg },
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[CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
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[CSR_MIE] = { "mie", any, read_mie, write_mie },
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@ -1906,20 +2038,23 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush },
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/* Machine Trap Handling */
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[CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch },
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[CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, NULL,
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read_mscratch_i128, write_mscratch_i128 },
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[CSR_MEPC] = { "mepc", any, read_mepc, write_mepc },
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[CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause },
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[CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
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[CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
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/* Supervisor Trap Setup */
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[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus },
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[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL,
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read_sstatus_i128 },
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[CSR_SIE] = { "sie", smode, read_sie, write_sie },
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[CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
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[CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
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/* Supervisor Trap Handling */
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[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
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[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL,
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read_sscratch_i128, write_sscratch_i128 },
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[CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc },
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[CSR_SCAUSE] = { "scause", smode, read_scause, write_scause },
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[CSR_STVAL] = { "stval", smode, read_stval, write_stval },
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