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Bug fixes.

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Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

Bug fixes.

# gpg: Signature made Mon 30 Jul 2018 13:00:39 BST
# gpg:                using RSA key BFFBD25F78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>"
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream:
  backends/cryptodev: remove dead code
  timer: remove replay clock probe in deadline calculation
  i386: implement MSR_SMI_COUNT for TCG
  i386: do not migrate MSR_SMI_COUNT on machine types <2.12

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-07-31 11:14:53 +01:00
commit 45a505d0a4
8 changed files with 14 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
backends/cryptodev-vhost-user.c
View File

@ -157,7 +157,6 @@ static void cryptodev_vhost_user_event(void *opaque, int event)
{
CryptoDevBackendVhostUser *s = opaque;
CryptoDevBackend *b = CRYPTODEV_BACKEND(s);
Error *err = NULL;
int queues = b->conf.peers.queues;
assert(queues < MAX_CRYPTO_QUEUE_NUM);
@ -174,10 +173,6 @@ static void cryptodev_vhost_user_event(void *opaque, int event)
cryptodev_vhost_user_stop(queues, s);
break;
}
if (err) {
error_report_err(err);
}
}
static void cryptodev_vhost_user_init(

4
include/hw/i386/pc.h
View File

@ -317,6 +317,10 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
#define PC_COMPAT_2_11 \
HW_COMPAT_2_11 \
{\
.driver = TYPE_X86_CPU,\
.property = "x-migrate-smi-count",\
.value = "off",\
},{\
.driver = "Skylake-Server" "-" TYPE_X86_CPU,\
.property = "clflushopt",\
.value = "off",\

2
target/i386/cpu.c
View File

@ -5435,6 +5435,8 @@ static Property x86_cpu_properties[] = {
false),
DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
true),
/*
* lecacy_cache defaults to true unless the CPU model provides its
* own cache information (see x86_cpu_load_def()).

1
target/i386/cpu.h
View File

@ -1379,6 +1379,7 @@ struct X86CPU {
bool expose_kvm;
bool expose_tcg;
bool migratable;
bool migrate_smi_count;
bool max_features; /* Enable all supported features automatically */
uint32_t apic_id;

2
target/i386/machine.c
View File

@ -400,7 +400,7 @@ static bool msr_smi_count_needed(void *opaque)
X86CPU *cpu = opaque;
CPUX86State *env = &cpu->env;
return env->msr_smi_count != 0;
return cpu->migrate_smi_count && env->msr_smi_count != 0;
}
static const VMStateDescription vmstate_msr_smi_count = {

3
target/i386/misc_helper.c
View File

@ -447,6 +447,9 @@ void helper_rdmsr(CPUX86State *env)
val = env->tsc_aux;
break;
#endif
case MSR_SMI_COUNT:
val = env->msr_smi_count;
break;
case MSR_MTRRphysBase(0):
case MSR_MTRRphysBase(1):
case MSR_MTRRphysBase(2):

1
target/i386/smm_helper.c
View File

@ -54,6 +54,7 @@ void do_smm_enter(X86CPU *cpu)
qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
env->msr_smi_count++;
env->hflags |= HF_SMM_MASK;
if (env->hflags2 & HF2_NMI_MASK) {
env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;

11
util/qemu-timer.c
View File

@ -578,17 +578,10 @@ int64_t timerlistgroup_deadline_ns(QEMUTimerListGroup *tlg)
{
int64_t deadline = -1;
QEMUClockType type;
bool play = replay_mode == REPLAY_MODE_PLAY;
for (type = 0; type < QEMU_CLOCK_MAX; type++) {
if (qemu_clock_use_for_deadline(type)) {
if (!play || type == QEMU_CLOCK_REALTIME) {
deadline = qemu_soonest_timeout(deadline,
timerlist_deadline_ns(tlg->tl[type]));
} else {
/* Read clock from the replay file and
do not calculate the deadline, based on virtual clock. */
qemu_clock_get_ns(type);
}
deadline = qemu_soonest_timeout(deadline,
timerlist_deadline_ns(tlg->tl[type]));
}
}
return deadline;