Bug fixes.
-----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAlte/ecUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroP5Egf+I5rWCZ5p3YGjP1HnSoWEoVNbeZvZ aXWtvYYBnL8B/nVJ11CynyZgwqHSDiCODHH29Q3Qiopu/yeEYEBc5NtsheND7cMi 2cXXT2uxHCenMx2oRBJ7H0580n7V1xC4HRbLsNhuk5G8VL0je/pdBylNWNlyEjlj 8K+J18IKYqSsrIpcHtnN5Y/hyvMoGTqi3dwUeTL6u8rFzulVVUo2q9G0+k9WybJD lK7f1gXJImTFxqAfyMIuJSRKI9PjZMwWT9pCJ4ie52l7EwL+hj0068EMziw7/AMd asUGd56PG9K/37h2WC/qcMdZnRHO/8EBvEMEHHmXKMEDFF2XSQXIoO4Qvw== =35+O -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging Bug fixes. # gpg: Signature made Mon 30 Jul 2018 13:00:39 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: backends/cryptodev: remove dead code timer: remove replay clock probe in deadline calculation i386: implement MSR_SMI_COUNT for TCG i386: do not migrate MSR_SMI_COUNT on machine types <2.12 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
45a505d0a4
@ -157,7 +157,6 @@ static void cryptodev_vhost_user_event(void *opaque, int event)
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{
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{
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CryptoDevBackendVhostUser *s = opaque;
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CryptoDevBackendVhostUser *s = opaque;
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CryptoDevBackend *b = CRYPTODEV_BACKEND(s);
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CryptoDevBackend *b = CRYPTODEV_BACKEND(s);
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Error *err = NULL;
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int queues = b->conf.peers.queues;
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int queues = b->conf.peers.queues;
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assert(queues < MAX_CRYPTO_QUEUE_NUM);
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assert(queues < MAX_CRYPTO_QUEUE_NUM);
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@ -174,10 +173,6 @@ static void cryptodev_vhost_user_event(void *opaque, int event)
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cryptodev_vhost_user_stop(queues, s);
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cryptodev_vhost_user_stop(queues, s);
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break;
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break;
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}
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}
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if (err) {
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error_report_err(err);
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}
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}
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}
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static void cryptodev_vhost_user_init(
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static void cryptodev_vhost_user_init(
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@ -317,6 +317,10 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
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#define PC_COMPAT_2_11 \
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#define PC_COMPAT_2_11 \
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HW_COMPAT_2_11 \
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HW_COMPAT_2_11 \
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{\
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{\
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.driver = TYPE_X86_CPU,\
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.property = "x-migrate-smi-count",\
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.value = "off",\
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},{\
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.driver = "Skylake-Server" "-" TYPE_X86_CPU,\
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.driver = "Skylake-Server" "-" TYPE_X86_CPU,\
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.property = "clflushopt",\
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.property = "clflushopt",\
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.value = "off",\
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.value = "off",\
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@ -5435,6 +5435,8 @@ static Property x86_cpu_properties[] = {
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false),
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false),
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DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
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DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
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DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
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DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
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DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
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true),
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/*
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/*
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* lecacy_cache defaults to true unless the CPU model provides its
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* lecacy_cache defaults to true unless the CPU model provides its
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* own cache information (see x86_cpu_load_def()).
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* own cache information (see x86_cpu_load_def()).
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@ -1379,6 +1379,7 @@ struct X86CPU {
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bool expose_kvm;
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bool expose_kvm;
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bool expose_tcg;
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bool expose_tcg;
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bool migratable;
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bool migratable;
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bool migrate_smi_count;
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bool max_features; /* Enable all supported features automatically */
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bool max_features; /* Enable all supported features automatically */
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uint32_t apic_id;
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uint32_t apic_id;
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@ -400,7 +400,7 @@ static bool msr_smi_count_needed(void *opaque)
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X86CPU *cpu = opaque;
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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CPUX86State *env = &cpu->env;
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return env->msr_smi_count != 0;
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return cpu->migrate_smi_count && env->msr_smi_count != 0;
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}
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}
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static const VMStateDescription vmstate_msr_smi_count = {
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static const VMStateDescription vmstate_msr_smi_count = {
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@ -447,6 +447,9 @@ void helper_rdmsr(CPUX86State *env)
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val = env->tsc_aux;
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val = env->tsc_aux;
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break;
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break;
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#endif
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#endif
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case MSR_SMI_COUNT:
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val = env->msr_smi_count;
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break;
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case MSR_MTRRphysBase(0):
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case MSR_MTRRphysBase(0):
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case MSR_MTRRphysBase(1):
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case MSR_MTRRphysBase(1):
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case MSR_MTRRphysBase(2):
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case MSR_MTRRphysBase(2):
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@ -54,6 +54,7 @@ void do_smm_enter(X86CPU *cpu)
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qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
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qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
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log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
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log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
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env->msr_smi_count++;
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env->hflags |= HF_SMM_MASK;
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env->hflags |= HF_SMM_MASK;
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if (env->hflags2 & HF2_NMI_MASK) {
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if (env->hflags2 & HF2_NMI_MASK) {
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env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
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env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
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@ -578,17 +578,10 @@ int64_t timerlistgroup_deadline_ns(QEMUTimerListGroup *tlg)
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{
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{
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int64_t deadline = -1;
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int64_t deadline = -1;
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QEMUClockType type;
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QEMUClockType type;
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bool play = replay_mode == REPLAY_MODE_PLAY;
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for (type = 0; type < QEMU_CLOCK_MAX; type++) {
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for (type = 0; type < QEMU_CLOCK_MAX; type++) {
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if (qemu_clock_use_for_deadline(type)) {
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if (qemu_clock_use_for_deadline(type)) {
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if (!play || type == QEMU_CLOCK_REALTIME) {
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deadline = qemu_soonest_timeout(deadline,
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deadline = qemu_soonest_timeout(deadline,
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timerlist_deadline_ns(tlg->tl[type]));
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timerlist_deadline_ns(tlg->tl[type]));
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} else {
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/* Read clock from the replay file and
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do not calculate the deadline, based on virtual clock. */
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qemu_clock_get_ns(type);
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}
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}
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}
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}
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}
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return deadline;
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return deadline;
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