target-sparc: Undo cpu_fpr rename.
Signed-off-by: Richard Henderson <rth@twiddle.net>
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ac11f7767f
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@ -63,7 +63,7 @@ static TCGv cpu_tmp0;
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static TCGv_i32 cpu_tmp32;
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static TCGv_i64 cpu_tmp64;
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/* Floating point registers */
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static TCGv_i32 cpu__fpr[TARGET_FPREGS];
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static TCGv_i32 cpu_fpr[TARGET_FPREGS];
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static target_ulong gen_opc_npc[OPC_BUF_SIZE];
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static target_ulong gen_opc_jump_pc[2];
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@ -126,12 +126,12 @@ static inline void gen_update_fprs_dirty(int rd)
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/* floating point registers moves */
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static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
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{
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return cpu__fpr[src];
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return cpu_fpr[src];
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}
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static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
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{
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tcg_gen_mov_i32(cpu__fpr[dst], v);
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tcg_gen_mov_i32(cpu_fpr[dst], v);
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gen_update_fprs_dirty(dst);
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}
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@ -146,13 +146,13 @@ static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
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src = DFPREG(src);
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#if TCG_TARGET_REG_BITS == 32
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tcg_gen_mov_i32(TCGV_HIGH(ret), cpu__fpr[src]);
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tcg_gen_mov_i32(TCGV_LOW(ret), cpu__fpr[src + 1]);
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tcg_gen_mov_i32(TCGV_HIGH(ret), cpu_fpr[src]);
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tcg_gen_mov_i32(TCGV_LOW(ret), cpu_fpr[src + 1]);
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#else
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{
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TCGv_i64 t = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(ret, cpu__fpr[src]);
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tcg_gen_extu_i32_i64(t, cpu__fpr[src + 1]);
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tcg_gen_extu_i32_i64(ret, cpu_fpr[src]);
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tcg_gen_extu_i32_i64(t, cpu_fpr[src + 1]);
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tcg_gen_shli_i64(ret, ret, 32);
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tcg_gen_or_i64(ret, ret, t);
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tcg_temp_free_i64(t);
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@ -173,9 +173,9 @@ static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
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tcg_gen_mov_i32(cpu__fpu[dst], TCGV_HIGH(v));
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tcg_gen_mov_i32(cpu__fpu[dst + 1], TCGV_LOW(v));
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#else
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tcg_gen_trunc_i64_i32(cpu__fpr[dst + 1], v);
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tcg_gen_trunc_i64_i32(cpu_fpr[dst + 1], v);
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tcg_gen_shri_i64(v, v, 32);
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tcg_gen_trunc_i64_i32(cpu__fpr[dst], v);
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tcg_gen_trunc_i64_i32(cpu_fpr[dst], v);
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#endif
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gen_update_fprs_dirty(dst);
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@ -188,37 +188,37 @@ static TCGv_i64 gen_dest_fpr_D(void)
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static void gen_op_load_fpr_QT0(unsigned int src)
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{
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tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +
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tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +
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offsetof(CPU_QuadU, l.upmost));
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tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
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tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
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offsetof(CPU_QuadU, l.upper));
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tcg_gen_st_i32(cpu__fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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offsetof(CPU_QuadU, l.lower));
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tcg_gen_st_i32(cpu__fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
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tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
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offsetof(CPU_QuadU, l.lowest));
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}
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static void gen_op_load_fpr_QT1(unsigned int src)
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{
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tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) +
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tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) +
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offsetof(CPU_QuadU, l.upmost));
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tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
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tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
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offsetof(CPU_QuadU, l.upper));
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tcg_gen_st_i32(cpu__fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
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tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
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offsetof(CPU_QuadU, l.lower));
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tcg_gen_st_i32(cpu__fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
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tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
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offsetof(CPU_QuadU, l.lowest));
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}
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static void gen_op_store_QT0_fpr(unsigned int dst)
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{
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tcg_gen_ld_i32(cpu__fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) +
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tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) +
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offsetof(CPU_QuadU, l.upmost));
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tcg_gen_ld_i32(cpu__fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
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tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
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offsetof(CPU_QuadU, l.upper));
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tcg_gen_ld_i32(cpu__fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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offsetof(CPU_QuadU, l.lower));
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tcg_gen_ld_i32(cpu__fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
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tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
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offsetof(CPU_QuadU, l.lowest));
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}
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@ -228,10 +228,10 @@ static void gen_move_Q(int rd, int rs)
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rd = QFPREG(rd);
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rs = QFPREG(rs);
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tcg_gen_mov_i32(cpu__fpr[rd], cpu__fpr[rs]);
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tcg_gen_mov_i32(cpu__fpr[rd + 1], cpu__fpr[rs + 1]);
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tcg_gen_mov_i32(cpu__fpr[rd + 2], cpu__fpr[rs + 2]);
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tcg_gen_mov_i32(cpu__fpr[rd + 3], cpu__fpr[rs + 3]);
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tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs]);
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tcg_gen_mov_i32(cpu_fpr[rd + 1], cpu_fpr[rs + 1]);
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tcg_gen_mov_i32(cpu_fpr[rd + 2], cpu_fpr[rs + 2]);
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tcg_gen_mov_i32(cpu_fpr[rd + 3], cpu_fpr[rs + 3]);
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gen_update_fprs_dirty(rd);
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}
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#endif
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@ -5251,9 +5251,9 @@ void gen_intermediate_code_init(CPUSPARCState *env)
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offsetof(CPUState, gregs[i]),
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gregnames[i]);
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for (i = 0; i < TARGET_FPREGS; i++)
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cpu__fpr[i] = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, fpr[i]),
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fregnames[i]);
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cpu_fpr[i] = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, fpr[i]),
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fregnames[i]);
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/* register helpers */
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