igb: Introduce qtest for igb device
This change is derived from qtest for e1000e device. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Acked-by: Thomas Huth <thuth@redhat.com> [Jason: make qtest work for win32 (only hotplug)] Signed-off-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
Akihiko Odaki
Jason Wang
parent
0caa7effcc
commit
45cb69bbd6
@ -2253,6 +2253,8 @@ igb
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M: Akihiko Odaki <akihiko.odaki@daynix.com>
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S: Maintained
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F: hw/net/igb*
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F: tests/qtest/igb-test.c
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F: tests/qtest/libqos/igb.c
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eepro100
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M: Stefan Weil <sw@weilnetz.de>
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@ -90,6 +90,11 @@ const generic_fuzz_config predefined_configs[] = {
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.args = "-M q35 -nodefaults "
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"-device e1000e,netdev=net0 -netdev user,id=net0",
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.objects = "e1000e",
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},{
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.name = "igb",
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.args = "-M q35 -nodefaults "
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"-device igb,netdev=net0 -netdev user,id=net0",
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.objects = "igb",
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},{
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.name = "cirrus-vga",
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.args = "-machine q35 -nodefaults -device cirrus-vga",
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256
tests/qtest/igb-test.c
Normal file
256
tests/qtest/igb-test.c
Normal file
@ -0,0 +1,256 @@
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/*
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* QTest testcase for igb NIC
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*
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* Copyright (c) 2022-2023 Red Hat, Inc.
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* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
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* Developed by Daynix Computing LTD (http://www.daynix.com)
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*
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* Authors:
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* Akihiko Odaki <akihiko.odaki@daynix.com>
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* Dmitry Fleytman <dmitry@daynix.com>
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* Leonid Bloch <leonid@daynix.com>
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* Yan Vugenfirer <yan@daynix.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "libqtest-single.h"
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#include "libqos/pci-pc.h"
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#include "net/eth.h"
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#include "qemu/sockets.h"
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#include "qemu/iov.h"
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#include "qemu/module.h"
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#include "qemu/bitops.h"
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#include "libqos/libqos-malloc.h"
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#include "libqos/e1000e.h"
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#include "hw/net/igb_regs.h"
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#ifndef _WIN32
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static const struct eth_header packet = {
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.h_dest = E1000E_ADDRESS,
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.h_source = E1000E_ADDRESS,
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};
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static void igb_send_verify(QE1000E *d, int *test_sockets, QGuestAllocator *alloc)
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{
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union e1000_adv_tx_desc descr;
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char buffer[64];
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int ret;
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uint32_t recv_len;
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/* Prepare test data buffer */
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uint64_t data = guest_alloc(alloc, sizeof(buffer));
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memwrite(data, &packet, sizeof(packet));
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/* Prepare TX descriptor */
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memset(&descr, 0, sizeof(descr));
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descr.read.buffer_addr = cpu_to_le64(data);
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descr.read.cmd_type_len = cpu_to_le32(E1000_TXD_CMD_RS |
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E1000_TXD_CMD_EOP |
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E1000_TXD_DTYP_D |
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sizeof(buffer));
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/* Put descriptor to the ring */
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e1000e_tx_ring_push(d, &descr);
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/* Wait for TX WB interrupt */
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e1000e_wait_isr(d, E1000E_TX0_MSG_ID);
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/* Check DD bit */
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g_assert_cmphex(le32_to_cpu(descr.wb.status) & E1000_TXD_STAT_DD, ==,
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E1000_TXD_STAT_DD);
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/* Check data sent to the backend */
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ret = recv(test_sockets[0], &recv_len, sizeof(recv_len), 0);
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g_assert_cmpint(ret, == , sizeof(recv_len));
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ret = recv(test_sockets[0], buffer, sizeof(buffer), 0);
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g_assert_cmpint(ret, ==, sizeof(buffer));
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g_assert_false(memcmp(buffer, &packet, sizeof(packet)));
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/* Free test data buffer */
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guest_free(alloc, data);
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}
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static void igb_receive_verify(QE1000E *d, int *test_sockets, QGuestAllocator *alloc)
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{
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union e1000_adv_rx_desc descr;
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struct eth_header test_iov = packet;
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int len = htonl(sizeof(packet));
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struct iovec iov[] = {
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{
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.iov_base = &len,
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.iov_len = sizeof(len),
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},{
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.iov_base = &test_iov,
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.iov_len = sizeof(packet),
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},
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};
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char buffer[64];
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int ret;
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/* Send a dummy packet to device's socket*/
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ret = iov_send(test_sockets[0], iov, 2, 0, sizeof(len) + sizeof(packet));
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g_assert_cmpint(ret, == , sizeof(packet) + sizeof(len));
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/* Prepare test data buffer */
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uint64_t data = guest_alloc(alloc, sizeof(buffer));
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/* Prepare RX descriptor */
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memset(&descr, 0, sizeof(descr));
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descr.read.pkt_addr = cpu_to_le64(data);
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/* Put descriptor to the ring */
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e1000e_rx_ring_push(d, &descr);
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/* Wait for TX WB interrupt */
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e1000e_wait_isr(d, E1000E_RX0_MSG_ID);
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/* Check DD bit */
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g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) &
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E1000_RXD_STAT_DD, ==, E1000_RXD_STAT_DD);
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/* Check data sent to the backend */
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memread(data, buffer, sizeof(buffer));
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g_assert_false(memcmp(buffer, &packet, sizeof(packet)));
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/* Free test data buffer */
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guest_free(alloc, data);
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}
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static void test_e1000e_init(void *obj, void *data, QGuestAllocator * alloc)
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{
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/* init does nothing */
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}
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static void test_igb_tx(void *obj, void *data, QGuestAllocator * alloc)
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{
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QE1000E_PCI *e1000e = obj;
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QE1000E *d = &e1000e->e1000e;
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QOSGraphObject *e_object = obj;
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QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
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/* FIXME: add spapr support */
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if (qpci_check_buggy_msi(dev)) {
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return;
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}
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igb_send_verify(d, data, alloc);
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}
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static void test_igb_rx(void *obj, void *data, QGuestAllocator * alloc)
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{
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QE1000E_PCI *e1000e = obj;
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QE1000E *d = &e1000e->e1000e;
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QOSGraphObject *e_object = obj;
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QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
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/* FIXME: add spapr support */
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if (qpci_check_buggy_msi(dev)) {
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return;
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}
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igb_receive_verify(d, data, alloc);
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}
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static void test_igb_multiple_transfers(void *obj, void *data,
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QGuestAllocator *alloc)
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{
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static const long iterations = 4 * 1024;
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long i;
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QE1000E_PCI *e1000e = obj;
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QE1000E *d = &e1000e->e1000e;
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QOSGraphObject *e_object = obj;
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QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
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/* FIXME: add spapr support */
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if (qpci_check_buggy_msi(dev)) {
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return;
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}
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for (i = 0; i < iterations; i++) {
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igb_send_verify(d, data, alloc);
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igb_receive_verify(d, data, alloc);
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}
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}
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static void data_test_clear(void *sockets)
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{
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int *test_sockets = sockets;
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close(test_sockets[0]);
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qos_invalidate_command_line();
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close(test_sockets[1]);
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g_free(test_sockets);
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}
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static void *data_test_init(GString *cmd_line, void *arg)
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{
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int *test_sockets = g_new(int, 2);
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int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets);
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g_assert_cmpint(ret, != , -1);
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g_string_append_printf(cmd_line, " -netdev socket,fd=%d,id=hs0 ",
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test_sockets[1]);
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g_test_queue_destroy(data_test_clear, test_sockets);
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return test_sockets;
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}
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#endif
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static void *data_test_init_no_socket(GString *cmd_line, void *arg)
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{
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g_string_append(cmd_line, " -netdev hubport,hubid=0,id=hs0 ");
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return arg;
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}
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static void test_igb_hotplug(void *obj, void *data, QGuestAllocator * alloc)
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{
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QTestState *qts = global_qtest; /* TODO: get rid of global_qtest here */
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QE1000E_PCI *dev = obj;
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if (dev->pci_dev.bus->not_hotpluggable) {
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g_test_skip("pci bus does not support hotplug");
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return;
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}
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qtest_qmp_device_add(qts, "igb", "igb_net", "{'addr': '0x06'}");
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qpci_unplug_acpi_device_test(qts, "igb_net", 0x06);
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}
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static void register_igb_test(void)
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{
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QOSGraphTestOptions opts = { 0 };
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#ifndef _WIN32
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opts.before = data_test_init,
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qos_add_test("init", "igb", test_e1000e_init, &opts);
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qos_add_test("tx", "igb", test_igb_tx, &opts);
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qos_add_test("rx", "igb", test_igb_rx, &opts);
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qos_add_test("multiple_transfers", "igb",
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test_igb_multiple_transfers, &opts);
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#endif
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opts.before = data_test_init_no_socket;
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qos_add_test("hotplug", "igb", test_igb_hotplug, &opts);
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}
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libqos_init(register_igb_test);
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185
tests/qtest/libqos/igb.c
Normal file
185
tests/qtest/libqos/igb.c
Normal file
@ -0,0 +1,185 @@
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/*
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* libqos driver framework
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*
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* Copyright (c) 2022-2023 Red Hat, Inc.
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* Copyright (c) 2018 Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2.1 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "qemu/osdep.h"
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#include "hw/net/igb_regs.h"
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#include "hw/net/mii.h"
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#include "hw/pci/pci_ids.h"
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#include "../libqtest.h"
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#include "pci-pc.h"
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#include "qemu/sockets.h"
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#include "qemu/iov.h"
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#include "qemu/module.h"
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#include "qemu/bitops.h"
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#include "libqos-malloc.h"
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#include "qgraph.h"
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#include "e1000e.h"
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#define IGB_IVAR_TEST_CFG \
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((E1000E_RX0_MSG_ID | E1000_IVAR_VALID) << (igb_ivar_entry_rx(0) * 8) | \
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((E1000E_TX0_MSG_ID | E1000_IVAR_VALID) << (igb_ivar_entry_tx(0) * 8)))
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#define E1000E_RING_LEN (0x1000)
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static void e1000e_foreach_callback(QPCIDevice *dev, int devfn, void *data)
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{
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QPCIDevice *res = data;
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memcpy(res, dev, sizeof(QPCIDevice));
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g_free(dev);
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}
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static void e1000e_pci_destructor(QOSGraphObject *obj)
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{
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QE1000E_PCI *epci = (QE1000E_PCI *) obj;
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qpci_iounmap(&epci->pci_dev, epci->mac_regs);
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qpci_msix_disable(&epci->pci_dev);
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}
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static void igb_pci_start_hw(QOSGraphObject *obj)
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{
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static const uint8_t address[] = E1000E_ADDRESS;
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QE1000E_PCI *d = (QE1000E_PCI *) obj;
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uint32_t val;
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/* Enable the device */
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qpci_device_enable(&d->pci_dev);
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/* Reset the device */
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val = e1000e_macreg_read(&d->e1000e, E1000_CTRL);
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e1000e_macreg_write(&d->e1000e, E1000_CTRL, val | E1000_CTRL_RST | E1000_CTRL_SLU);
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/* Setup link */
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e1000e_macreg_write(&d->e1000e, E1000_MDIC,
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MII_BMCR_AUTOEN | MII_BMCR_ANRESTART |
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(MII_BMCR << E1000_MDIC_REG_SHIFT) |
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(1 << E1000_MDIC_PHY_SHIFT) |
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E1000_MDIC_OP_WRITE);
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qtest_clock_step(d->pci_dev.bus->qts, 900000000);
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/* Enable and configure MSI-X */
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qpci_msix_enable(&d->pci_dev);
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e1000e_macreg_write(&d->e1000e, E1000_IVAR0, IGB_IVAR_TEST_CFG);
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/* Check the device link status */
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val = e1000e_macreg_read(&d->e1000e, E1000_STATUS);
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g_assert_cmphex(val & E1000_STATUS_LU, ==, E1000_STATUS_LU);
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/* Initialize TX/RX logic */
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e1000e_macreg_write(&d->e1000e, E1000_RCTL, 0);
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e1000e_macreg_write(&d->e1000e, E1000_TCTL, 0);
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e1000e_macreg_write(&d->e1000e, E1000_TDBAL(0),
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(uint32_t) d->e1000e.tx_ring);
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e1000e_macreg_write(&d->e1000e, E1000_TDBAH(0),
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(uint32_t) (d->e1000e.tx_ring >> 32));
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e1000e_macreg_write(&d->e1000e, E1000_TDLEN(0), E1000E_RING_LEN);
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e1000e_macreg_write(&d->e1000e, E1000_TDT(0), 0);
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e1000e_macreg_write(&d->e1000e, E1000_TDH(0), 0);
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/* Enable transmit */
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e1000e_macreg_write(&d->e1000e, E1000_TCTL, E1000_TCTL_EN);
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e1000e_macreg_write(&d->e1000e, E1000_RDBAL(0),
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(uint32_t)d->e1000e.rx_ring);
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e1000e_macreg_write(&d->e1000e, E1000_RDBAH(0),
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(uint32_t)(d->e1000e.rx_ring >> 32));
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e1000e_macreg_write(&d->e1000e, E1000_RDLEN(0), E1000E_RING_LEN);
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e1000e_macreg_write(&d->e1000e, E1000_RDT(0), 0);
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e1000e_macreg_write(&d->e1000e, E1000_RDH(0), 0);
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e1000e_macreg_write(&d->e1000e, E1000_RA,
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le32_to_cpu(*(uint32_t *)address));
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e1000e_macreg_write(&d->e1000e, E1000_RA + 4,
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E1000_RAH_AV | E1000_RAH_POOL_1 |
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le16_to_cpu(*(uint16_t *)(address + 4)));
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/* Enable receive */
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e1000e_macreg_write(&d->e1000e, E1000_RFCTL, E1000_RFCTL_EXTEN);
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e1000e_macreg_write(&d->e1000e, E1000_RCTL, E1000_RCTL_EN);
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/* Enable all interrupts */
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e1000e_macreg_write(&d->e1000e, E1000_IMS, 0xFFFFFFFF);
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e1000e_macreg_write(&d->e1000e, E1000_EIMS, 0xFFFFFFFF);
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}
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static void *igb_pci_get_driver(void *obj, const char *interface)
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{
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QE1000E_PCI *epci = obj;
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if (!g_strcmp0(interface, "igb-if")) {
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return &epci->e1000e;
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}
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/* implicit contains */
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if (!g_strcmp0(interface, "pci-device")) {
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return &epci->pci_dev;
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}
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fprintf(stderr, "%s not present in igb\n", interface);
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g_assert_not_reached();
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}
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static void *igb_pci_create(void *pci_bus, QGuestAllocator *alloc, void *addr)
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{
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QE1000E_PCI *d = g_new0(QE1000E_PCI, 1);
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||||
QPCIBus *bus = pci_bus;
|
||||
QPCIAddress *address = addr;
|
||||
|
||||
qpci_device_foreach(bus, address->vendor_id, address->device_id,
|
||||
e1000e_foreach_callback, &d->pci_dev);
|
||||
|
||||
/* Map BAR0 (mac registers) */
|
||||
d->mac_regs = qpci_iomap(&d->pci_dev, 0, NULL);
|
||||
|
||||
/* Allocate and setup TX ring */
|
||||
d->e1000e.tx_ring = guest_alloc(alloc, E1000E_RING_LEN);
|
||||
g_assert(d->e1000e.tx_ring != 0);
|
||||
|
||||
/* Allocate and setup RX ring */
|
||||
d->e1000e.rx_ring = guest_alloc(alloc, E1000E_RING_LEN);
|
||||
g_assert(d->e1000e.rx_ring != 0);
|
||||
|
||||
d->obj.get_driver = igb_pci_get_driver;
|
||||
d->obj.start_hw = igb_pci_start_hw;
|
||||
d->obj.destructor = e1000e_pci_destructor;
|
||||
|
||||
return &d->obj;
|
||||
}
|
||||
|
||||
static void igb_register_nodes(void)
|
||||
{
|
||||
QPCIAddress addr = {
|
||||
.vendor_id = PCI_VENDOR_ID_INTEL,
|
||||
.device_id = E1000_DEV_ID_82576,
|
||||
};
|
||||
|
||||
/*
|
||||
* FIXME: every test using this node needs to setup a -netdev socket,id=hs0
|
||||
* otherwise QEMU is not going to start
|
||||
*/
|
||||
QOSGraphEdgeOptions opts = {
|
||||
.extra_device_opts = "netdev=hs0",
|
||||
};
|
||||
add_qpci_address(&opts, &addr);
|
||||
|
||||
qos_node_create_driver("igb", igb_pci_create);
|
||||
qos_node_consumes("igb", "pci-bus", &opts);
|
||||
}
|
||||
|
||||
libqos_init(igb_register_nodes);
|
||||
@ -30,6 +30,7 @@ libqos_srcs = files(
|
||||
'i2c.c',
|
||||
'i2c-imx.c',
|
||||
'i2c-omap.c',
|
||||
'igb.c',
|
||||
'sdhci.c',
|
||||
'tpci200.c',
|
||||
'virtio.c',
|
||||
|
||||
@ -259,6 +259,7 @@ qos_test_ss.add(
|
||||
'virtio-scsi-test.c',
|
||||
'virtio-iommu-test.c',
|
||||
'vmxnet3-test.c',
|
||||
'igb-test.c',
|
||||
)
|
||||
|
||||
if config_all_devices.has_key('CONFIG_VIRTIO_SERIAL')
|
||||
|
||||
Loading…
Reference in New Issue
Block a user