i.MX: implement a more correct version of EPIT timer.
This patch is providing a complete version of the EPIT timer. Note, however that the GPT timer in the same file is still not complete. Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net> Message-id: 1365624982-15647-1-git-send-email-jcd@tribudubois.net Reviewed-by: Peter Chubb <peter.chubb@nicta.com.au> [PMM: wrapped an overly long line] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jean-Christophe DUBOIS
Peter Maydell
parent
743bddb4b3
commit
462566fc5e
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@ -95,6 +95,10 @@ typedef struct {
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uint32_t sr;
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uint32_t ir;
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uint32_t ocr1;
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uint32_t ocr2;
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uint32_t ocr3;
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uint32_t icr1;
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uint32_t icr2;
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uint32_t cnt;
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uint32_t waiting_rov;
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@ -103,15 +107,19 @@ typedef struct {
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static const VMStateDescription vmstate_imx_timerg = {
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.name = "imx-timerg",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cr, IMXTimerGState),
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VMSTATE_UINT32(pr, IMXTimerGState),
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VMSTATE_UINT32(sr, IMXTimerGState),
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VMSTATE_UINT32(ir, IMXTimerGState),
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VMSTATE_UINT32(ocr1, IMXTimerGState),
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VMSTATE_UINT32(ocr2, IMXTimerGState),
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VMSTATE_UINT32(ocr3, IMXTimerGState),
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VMSTATE_UINT32(icr1, IMXTimerGState),
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VMSTATE_UINT32(icr2, IMXTimerGState),
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VMSTATE_UINT32(cnt, IMXTimerGState),
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VMSTATE_UINT32(waiting_rov, IMXTimerGState),
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VMSTATE_PTIMER(timer, IMXTimerGState),
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@ -156,7 +164,6 @@ static void imx_timerg_update(IMXTimerGState *s)
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s->ir & GPT_SR_ROV ? "ROV" : "",
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s->cr & GPT_CR_EN ? "CR_EN" : "Not Enabled");
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qemu_set_irq(s->irq, (s->cr & GPT_CR_EN) && flags);
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}
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@ -221,6 +228,21 @@ static uint64_t imx_timerg_read(void *opaque, hwaddr offset,
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DPRINTF(" ocr1 = %x\n", s->ocr1);
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return s->ocr1;
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case 5: /* Output Compare Register 2 */
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DPRINTF(" ocr2 = %x\n", s->ocr2);
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return s->ocr2;
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case 6: /* Output Compare Register 3 */
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DPRINTF(" ocr3 = %x\n", s->ocr3);
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return s->ocr3;
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case 7: /* input Capture Register 1 */
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DPRINTF(" icr1 = %x\n", s->icr1);
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return s->icr1;
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case 8: /* input Capture Register 2 */
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DPRINTF(" icr2 = %x\n", s->icr2);
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return s->icr2;
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case 9: /* cnt */
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imx_timerg_update_counts(s);
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@ -230,6 +252,7 @@ static uint64_t imx_timerg_read(void *opaque, hwaddr offset,
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IPRINTF("imx_timerg_read: Bad offset %x\n",
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(int)offset >> 2);
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return 0;
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}
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@ -240,14 +263,20 @@ static void imx_timerg_reset(DeviceState *dev)
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/*
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* Soft reset doesn't touch some bits; hard reset clears them
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*/
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s->cr &= ~(GPT_CR_EN|GPT_CR_DOZEN|GPT_CR_WAITEN|GPT_CR_DBGEN);
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s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN|
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GPT_CR_WAITEN|GPT_CR_DBGEN);
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s->sr = 0;
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s->pr = 0;
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s->ir = 0;
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s->cnt = 0;
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s->ocr1 = TIMER_MAX;
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s->ocr2 = TIMER_MAX;
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s->ocr3 = TIMER_MAX;
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s->icr1 = 0;
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s->icr2 = 0;
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ptimer_stop(s->timer);
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ptimer_set_limit(s->timer, TIMER_MAX, 1);
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ptimer_set_count(s->timer, TIMER_MAX);
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imx_timerg_set_freq(s);
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}
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@ -323,6 +352,8 @@ static void imx_timerg_write(void *opaque, hwaddr offset,
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s->ocr1 = value;
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return;
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case 5: /* OCR2 -- output compare register */
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case 6: /* OCR3 -- output compare register */
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default:
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IPRINTF("imx_timerg_write: Bad offset %x\n",
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(int)offset >> 2);
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@ -411,7 +442,7 @@ static int imx_timerg_init(SysBusDevice *dev)
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#define CR_SWR (1 << 16)
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#define CR_IOVW (1 << 17)
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#define CR_DBGEN (1 << 18)
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#define CR_EPIT (1 << 19)
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#define CR_WAITEN (1 << 19)
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#define CR_DOZEN (1 << 20)
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#define CR_STOPEN (1 << 21)
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#define CR_CLKSRC_SHIFT (24)
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@ -423,24 +454,26 @@ static int imx_timerg_init(SysBusDevice *dev)
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* These are typical.
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*/
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static const IMXClk imx_timerp_clocks[] = {
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0, /* disabled */
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IPG, /* ipg_clk, ~532MHz */
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IPG, /* ipg_clk_highfreq */
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CLK_32k, /* ipg_clk_32k -- ~32kHz */
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0, /* 00 disabled */
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IPG, /* 01 ipg_clk, ~532MHz */
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IPG, /* 10 ipg_clk_highfreq */
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CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */
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};
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typedef struct {
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SysBusDevice busdev;
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ptimer_state *timer;
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ptimer_state *timer_reload;
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ptimer_state *timer_cmp;
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MemoryRegion iomem;
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DeviceState *ccm;
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uint32_t cr;
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uint32_t sr;
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uint32_t lr;
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uint32_t cmp;
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uint32_t cnt;
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uint32_t freq;
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int int_level;
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qemu_irq irq;
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} IMXTimerPState;
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@ -449,56 +482,13 @@ typedef struct {
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*/
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static void imx_timerp_update(IMXTimerPState *s)
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{
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if (s->int_level && (s->cr & CR_OCIEN)) {
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if (s->sr && (s->cr & CR_OCIEN)) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static void imx_timerp_reset(DeviceState *dev)
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{
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IMXTimerPState *s = container_of(dev, IMXTimerPState, busdev.qdev);
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s->cr = 0;
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s->lr = TIMER_MAX;
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s->int_level = 0;
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s->cmp = 0;
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ptimer_stop(s->timer);
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ptimer_set_count(s->timer, TIMER_MAX);
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}
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static uint64_t imx_timerp_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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IMXTimerPState *s = (IMXTimerPState *)opaque;
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DPRINTF("p-read(offset=%x)", offset >> 2);
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switch (offset >> 2) {
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case 0: /* Control Register */
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DPRINTF("cr %x\n", s->cr);
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return s->cr;
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case 1: /* Status Register */
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DPRINTF("int_level %x\n", s->int_level);
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return s->int_level;
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case 2: /* LR - ticks*/
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DPRINTF("lr %x\n", s->lr);
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return s->lr;
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case 3: /* CMP */
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DPRINTF("cmp %x\n", s->cmp);
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return s->cmp;
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case 4: /* CNT */
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return ptimer_get_count(s->timer);
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}
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IPRINTF("imx_timerp_read: Bad offset %x\n",
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(int)offset >> 2);
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return 0;
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}
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static void set_timerp_freq(IMXTimerPState *s)
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{
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int clksrc;
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@ -513,7 +503,91 @@ static void set_timerp_freq(IMXTimerPState *s)
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DPRINTF("Setting ptimer frequency to %u\n", freq);
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if (freq) {
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ptimer_set_freq(s->timer, freq);
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ptimer_set_freq(s->timer_reload, freq);
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ptimer_set_freq(s->timer_cmp, freq);
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}
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}
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static void imx_timerp_reset(DeviceState *dev)
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{
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IMXTimerPState *s = container_of(dev, IMXTimerPState, busdev.qdev);
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/*
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* Soft reset doesn't touch some bits; hard reset clears them
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*/
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s->cr &= ~(CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
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s->sr = 0;
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s->lr = TIMER_MAX;
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s->cmp = 0;
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s->cnt = 0;
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/* stop both timers */
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ptimer_stop(s->timer_cmp);
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ptimer_stop(s->timer_reload);
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/* compute new frequency */
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set_timerp_freq(s);
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/* init both timers to TIMER_MAX */
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ptimer_set_limit(s->timer_cmp, TIMER_MAX, 1);
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ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
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if (s->freq && (s->cr & CR_EN)) {
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/* if the timer is still enabled, restart it */
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ptimer_run(s->timer_reload, 1);
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}
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}
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static uint32_t imx_timerp_update_counts(IMXTimerPState *s)
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{
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s->cnt = ptimer_get_count(s->timer_reload);
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return s->cnt;
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}
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static uint64_t imx_timerp_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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IMXTimerPState *s = (IMXTimerPState *)opaque;
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DPRINTF("p-read(offset=%x)", offset >> 2);
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switch (offset >> 2) {
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case 0: /* Control Register */
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DPRINTF("cr %x\n", s->cr);
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return s->cr;
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case 1: /* Status Register */
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DPRINTF("sr %x\n", s->sr);
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return s->sr;
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case 2: /* LR - ticks*/
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DPRINTF("lr %x\n", s->lr);
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return s->lr;
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case 3: /* CMP */
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DPRINTF("cmp %x\n", s->cmp);
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return s->cmp;
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case 4: /* CNT */
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imx_timerp_update_counts(s);
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DPRINTF(" cnt = %x\n", s->cnt);
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return s->cnt;
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}
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IPRINTF("imx_timerp_read: Bad offset %x\n",
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(int)offset >> 2);
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return 0;
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}
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static void imx_reload_compare_timer(IMXTimerPState *s)
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{
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if ((s->cr & CR_OCIEN) && s->cmp) {
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/* if the compare feature is on */
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uint32_t tmp = imx_timerp_update_counts(s);
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if (tmp > s->cmp) {
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/* reinit the cmp timer if required */
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ptimer_set_count(s->timer_cmp, tmp - s->cmp);
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if ((s->cr & CR_EN)) {
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/* Restart the cmp timer if required */
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ptimer_run(s->timer_cmp, 0);
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}
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}
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}
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}
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@ -526,40 +600,62 @@ static void imx_timerp_write(void *opaque, hwaddr offset,
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switch (offset >> 2) {
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case 0: /* CR */
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if (value & CR_SWR) {
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imx_timerp_reset(&s->busdev.qdev);
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value &= ~CR_SWR;
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}
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s->cr = value & 0x03ffffff;
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set_timerp_freq(s);
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if (s->cr & CR_SWR) {
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/* handle the reset */
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imx_timerp_reset(&s->busdev.qdev);
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} else {
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set_timerp_freq(s);
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}
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if (s->freq && (s->cr & CR_EN)) {
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if (!(s->cr & CR_ENMOD)) {
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ptimer_set_count(s->timer, s->lr);
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if (s->cr & CR_ENMOD) {
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if (s->cr & CR_RLD) {
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ptimer_set_limit(s->timer_reload, s->lr, 1);
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} else {
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ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
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}
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}
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ptimer_run(s->timer, 0);
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imx_reload_compare_timer(s);
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ptimer_run(s->timer_reload, 1);
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} else {
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ptimer_stop(s->timer);
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/* stop both timers */
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ptimer_stop(s->timer_reload);
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ptimer_stop(s->timer_cmp);
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}
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break;
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case 1: /* SR - ACK*/
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s->int_level = 0;
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imx_timerp_update(s);
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/* writing 1 to OCIF clear the OCIF bit */
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if (value & 0x01) {
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s->sr = 0;
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imx_timerp_update(s);
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}
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break;
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case 2: /* LR - set ticks */
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s->lr = value;
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ptimer_set_limit(s->timer, value, !!(s->cr & CR_IOVW));
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if (s->cr & CR_RLD) {
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/* Also set the limit if the LRD bit is set */
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/* If IOVW bit is set then set the timer value */
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ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
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} else if (s->cr & CR_IOVW) {
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/* If IOVW bit is set then set the timer value */
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ptimer_set_count(s->timer_reload, s->lr);
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}
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imx_reload_compare_timer(s);
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break;
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case 3: /* CMP */
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s->cmp = value;
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if (value) {
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IPRINTF(
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"Values for EPIT comparison other than zero not supported\n"
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);
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}
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imx_reload_compare_timer(s);
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break;
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default:
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@ -568,16 +664,50 @@ static void imx_timerp_write(void *opaque, hwaddr offset,
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}
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}
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static void imx_timerp_tick(void *opaque)
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static void imx_timerp_reload(void *opaque)
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{
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IMXTimerPState *s = (IMXTimerPState *)opaque;
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DPRINTF("imxp tick\n");
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if (!(s->cr & CR_RLD)) {
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ptimer_set_count(s->timer, TIMER_MAX);
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DPRINTF("imxp reload\n");
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if (!(s->cr & CR_EN)) {
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return;
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}
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if (s->cr & CR_RLD) {
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ptimer_set_limit(s->timer_reload, s->lr, 1);
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} else {
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ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
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}
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if (s->cr & CR_OCIEN) {
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/* if compare register is 0 then we handle the interrupt here */
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if (s->cmp == 0) {
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s->sr = 1;
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imx_timerp_update(s);
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} else if (s->cmp <= s->lr) {
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/* We should launch the compare register */
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ptimer_set_count(s->timer_cmp, s->lr - s->cmp);
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ptimer_run(s->timer_cmp, 0);
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} else {
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IPRINTF("imxp reload: s->lr < s->cmp\n");
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}
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}
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}
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static void imx_timerp_cmp(void *opaque)
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{
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IMXTimerPState *s = (IMXTimerPState *)opaque;
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DPRINTF("imxp compare\n");
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ptimer_stop(s->timer_cmp);
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/* compare register is not 0 */
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if (s->cmp) {
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s->sr = 1;
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imx_timerp_update(s);
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}
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s->int_level = 1;
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imx_timerp_update(s);
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}
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void imx_timerp_create(const hwaddr addr,
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@ -600,16 +730,18 @@ static const MemoryRegionOps imx_timerp_ops = {
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static const VMStateDescription vmstate_imx_timerp = {
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.name = "imx-timerp",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cr, IMXTimerPState),
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VMSTATE_UINT32(sr, IMXTimerPState),
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VMSTATE_UINT32(lr, IMXTimerPState),
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VMSTATE_UINT32(cmp, IMXTimerPState),
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VMSTATE_UINT32(cnt, IMXTimerPState),
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VMSTATE_UINT32(freq, IMXTimerPState),
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VMSTATE_INT32(int_level, IMXTimerPState),
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VMSTATE_PTIMER(timer, IMXTimerPState),
|
||||
VMSTATE_PTIMER(timer_reload, IMXTimerPState),
|
||||
VMSTATE_PTIMER(timer_cmp, IMXTimerPState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
|
@ -620,15 +752,17 @@ static int imx_timerp_init(SysBusDevice *dev)
|
|||
QEMUBH *bh;
|
||||
|
||||
DPRINTF("imx_timerp_init\n");
|
||||
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
memory_region_init_io(&s->iomem, &imx_timerp_ops,
|
||||
s, "imxp-timer",
|
||||
0x00001000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
bh = qemu_bh_new(imx_timerp_tick, s);
|
||||
s->timer = ptimer_init(bh);
|
||||
bh = qemu_bh_new(imx_timerp_reload, s);
|
||||
s->timer_reload = ptimer_init(bh);
|
||||
|
||||
bh = qemu_bh_new(imx_timerp_cmp, s);
|
||||
s->timer_cmp = ptimer_init(bh);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue