target/arm: Use insn_start from DisasContextBase
To keep the multiple update check, replace insn_start with insn_start_updated. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -14179,7 +14179,7 @@ static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
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pc_arg &= ~TARGET_PAGE_MASK;
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}
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tcg_gen_insn_start(pc_arg, 0, 0);
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dc->insn_start = tcg_last_op();
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dc->insn_start_updated = false;
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}
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static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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@ -9273,7 +9273,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
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condexec_bits = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
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}
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tcg_gen_insn_start(pc_arg, condexec_bits, 0);
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dc->insn_start = tcg_last_op();
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dc->insn_start_updated = false;
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}
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static bool arm_check_kernelpage(DisasContext *dc)
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@ -165,10 +165,10 @@ typedef struct DisasContext {
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uint8_t gm_blocksize;
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/* True if this page is guarded. */
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bool guarded_page;
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/* True if the current insn_start has been updated. */
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bool insn_start_updated;
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/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
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int c15_cpar;
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/* TCG op of the current insn_start. */
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TCGOp *insn_start;
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/* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */
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uint32_t nv2_redirect_offset;
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} DisasContext;
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@ -276,10 +276,10 @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
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syn &= ARM_INSN_START_WORD2_MASK;
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syn >>= ARM_INSN_START_WORD2_SHIFT;
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/* We check and clear insn_start_idx to catch multiple updates. */
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assert(s->insn_start != NULL);
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tcg_set_insn_start_param(s->insn_start, 2, syn);
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s->insn_start = NULL;
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/* Check for multiple updates. */
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assert(!s->insn_start_updated);
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s->insn_start_updated = true;
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tcg_set_insn_start_param(s->base.insn_start, 2, syn);
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}
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static inline int curr_insn_len(DisasContext *s)
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