tcg/aarch64: Support INDEX_op_extract2_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -77,7 +77,7 @@ typedef enum {
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_extract2_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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@ -114,7 +114,7 @@ typedef enum {
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_extract2_i64 1
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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@ -2058,6 +2058,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
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break;
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case INDEX_op_extract2_i64:
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case INDEX_op_extract2_i32:
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tcg_out_extr(s, ext, a0, a1, a2, args[3]);
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break;
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case INDEX_op_add2_i32:
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tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
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(int32_t)args[4], args[5], const_args[4],
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@ -2300,6 +2305,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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= { .args_ct_str = { "r", "r", "rAL" } };
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static const TCGTargetOpDef dep
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= { .args_ct_str = { "r", "0", "rZ" } };
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static const TCGTargetOpDef ext2
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= { .args_ct_str = { "r", "rZ", "rZ" } };
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static const TCGTargetOpDef movc
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= { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
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static const TCGTargetOpDef add2
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@ -2430,6 +2437,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_deposit_i64:
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return &dep;
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case INDEX_op_extract2_i32:
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case INDEX_op_extract2_i64:
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return &ext2;
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case INDEX_op_add2_i32:
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case INDEX_op_add2_i64:
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case INDEX_op_sub2_i32:
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