hw/cxl/device: Implement basic mailbox (8.2.8.4)
This is the beginning of implementing mailbox support for CXL 2.0 devices. The implementation recognizes when the doorbell is rung, handles the command/payload, clears the doorbell while returning error codes and data. Generally the mailbox mechanism is designed to permit communication between the host OS and the firmware running on the device. For our purposes, we emulate both the firmware, implemented primarily in cxl-mailbox-utils.c, and the hardware. No commands are implemented yet. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220429144110.25167-7-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Ben Widawsky
Michael S. Tsirkin
parent
6364adacdf
commit
464e14ac43
@ -44,6 +44,108 @@ static uint64_t dev_reg_read(void *opaque, hwaddr offset, unsigned size)
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return 0;
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}
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static uint64_t mailbox_reg_read(void *opaque, hwaddr offset, unsigned size)
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{
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CXLDeviceState *cxl_dstate = opaque;
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switch (size) {
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case 1:
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return cxl_dstate->mbox_reg_state[offset];
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case 2:
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return cxl_dstate->mbox_reg_state16[offset / size];
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case 4:
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return cxl_dstate->mbox_reg_state32[offset / size];
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case 8:
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return cxl_dstate->mbox_reg_state64[offset / size];
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default:
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g_assert_not_reached();
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}
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}
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static void mailbox_mem_writel(uint32_t *reg_state, hwaddr offset,
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uint64_t value)
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{
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switch (offset) {
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case A_CXL_DEV_MAILBOX_CTRL:
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/* fallthrough */
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case A_CXL_DEV_MAILBOX_CAP:
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/* RO register */
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s Unexpected 32-bit access to 0x%" PRIx64 " (WI)\n",
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__func__, offset);
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return;
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}
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reg_state[offset / sizeof(*reg_state)] = value;
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}
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static void mailbox_mem_writeq(uint64_t *reg_state, hwaddr offset,
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uint64_t value)
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{
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switch (offset) {
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case A_CXL_DEV_MAILBOX_CMD:
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break;
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case A_CXL_DEV_BG_CMD_STS:
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/* BG not supported */
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/* fallthrough */
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case A_CXL_DEV_MAILBOX_STS:
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/* Read only register, will get updated by the state machine */
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return;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s Unexpected 64-bit access to 0x%" PRIx64 " (WI)\n",
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__func__, offset);
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return;
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}
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reg_state[offset / sizeof(*reg_state)] = value;
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}
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static void mailbox_reg_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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CXLDeviceState *cxl_dstate = opaque;
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if (offset >= A_CXL_DEV_CMD_PAYLOAD) {
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memcpy(cxl_dstate->mbox_reg_state + offset, &value, size);
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return;
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}
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switch (size) {
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case 4:
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mailbox_mem_writel(cxl_dstate->mbox_reg_state32, offset, value);
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break;
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case 8:
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mailbox_mem_writeq(cxl_dstate->mbox_reg_state64, offset, value);
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break;
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default:
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g_assert_not_reached();
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}
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if (ARRAY_FIELD_EX32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL,
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DOORBELL)) {
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cxl_process_mailbox(cxl_dstate);
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}
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}
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static const MemoryRegionOps mailbox_ops = {
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.read = mailbox_reg_read,
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.write = mailbox_reg_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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.unaligned = false,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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static const MemoryRegionOps dev_ops = {
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.read = dev_reg_read,
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.write = NULL, /* status register is read only */
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@ -84,20 +186,33 @@ void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstate)
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"cap-array", CXL_CAPS_SIZE);
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memory_region_init_io(&cxl_dstate->device, obj, &dev_ops, cxl_dstate,
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"device-status", CXL_DEVICE_STATUS_REGISTERS_LENGTH);
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memory_region_init_io(&cxl_dstate->mailbox, obj, &mailbox_ops, cxl_dstate,
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"mailbox", CXL_MAILBOX_REGISTERS_LENGTH);
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memory_region_add_subregion(&cxl_dstate->device_registers, 0,
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&cxl_dstate->caps);
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memory_region_add_subregion(&cxl_dstate->device_registers,
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CXL_DEVICE_STATUS_REGISTERS_OFFSET,
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&cxl_dstate->device);
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memory_region_add_subregion(&cxl_dstate->device_registers,
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CXL_MAILBOX_REGISTERS_OFFSET,
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&cxl_dstate->mailbox);
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}
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static void device_reg_init_common(CXLDeviceState *cxl_dstate) { }
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static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate)
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{
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/* 2048 payload size, with no interrupt or background support */
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ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
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PAYLOAD_SIZE, CXL_MAILBOX_PAYLOAD_SHIFT);
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cxl_dstate->payload_size = CXL_MAILBOX_MAX_PAYLOAD_SIZE;
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}
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void cxl_device_register_init_common(CXLDeviceState *cxl_dstate)
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{
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uint64_t *cap_hdrs = cxl_dstate->caps_reg_state64;
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const int cap_count = 1;
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const int cap_count = 2;
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/* CXL Device Capabilities Array Register */
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ARRAY_FIELD_DP64(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0);
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@ -106,4 +221,9 @@ void cxl_device_register_init_common(CXLDeviceState *cxl_dstate)
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cxl_device_cap_init(cxl_dstate, DEVICE_STATUS, 1);
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device_reg_init_common(cxl_dstate);
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cxl_device_cap_init(cxl_dstate, MAILBOX, 2);
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mailbox_reg_init_common(cxl_dstate);
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assert(cxl_initialize_mailbox(cxl_dstate) == 0);
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}
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164
hw/cxl/cxl-mailbox-utils.c
Normal file
164
hw/cxl/cxl-mailbox-utils.c
Normal file
@ -0,0 +1,164 @@
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/*
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* CXL Utility library for mailbox interface
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*
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* Copyright(C) 2020 Intel Corporation.
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/cxl/cxl.h"
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#include "hw/pci/pci.h"
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#include "qemu/log.h"
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#include "qemu/uuid.h"
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/*
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* How to add a new command, example. The command set FOO, with cmd BAR.
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* 1. Add the command set and cmd to the enum.
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* FOO = 0x7f,
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* #define BAR 0
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* 2. Implement the handler
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* static ret_code cmd_foo_bar(struct cxl_cmd *cmd,
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* CXLDeviceState *cxl_dstate, uint16_t *len)
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* 3. Add the command to the cxl_cmd_set[][]
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* [FOO][BAR] = { "FOO_BAR", cmd_foo_bar, x, y },
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* 4. Implement your handler
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* define_mailbox_handler(FOO_BAR) { ... return CXL_MBOX_SUCCESS; }
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*
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*
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* Writing the handler:
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* The handler will provide the &struct cxl_cmd, the &CXLDeviceState, and the
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* in/out length of the payload. The handler is responsible for consuming the
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* payload from cmd->payload and operating upon it as necessary. It must then
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* fill the output data into cmd->payload (overwriting what was there),
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* setting the length, and returning a valid return code.
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*
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* XXX: The handler need not worry about endianess. The payload is read out of
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* a register interface that already deals with it.
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*/
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/* 8.2.8.4.5.1 Command Return Codes */
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typedef enum {
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CXL_MBOX_SUCCESS = 0x0,
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CXL_MBOX_BG_STARTED = 0x1,
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CXL_MBOX_INVALID_INPUT = 0x2,
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CXL_MBOX_UNSUPPORTED = 0x3,
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CXL_MBOX_INTERNAL_ERROR = 0x4,
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CXL_MBOX_RETRY_REQUIRED = 0x5,
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CXL_MBOX_BUSY = 0x6,
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CXL_MBOX_MEDIA_DISABLED = 0x7,
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CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8,
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CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9,
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CXL_MBOX_FW_AUTH_FAILED = 0xa,
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CXL_MBOX_FW_INVALID_SLOT = 0xb,
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CXL_MBOX_FW_ROLLEDBACK = 0xc,
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CXL_MBOX_FW_REST_REQD = 0xd,
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CXL_MBOX_INVALID_HANDLE = 0xe,
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CXL_MBOX_INVALID_PA = 0xf,
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CXL_MBOX_INJECT_POISON_LIMIT = 0x10,
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CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11,
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CXL_MBOX_ABORTED = 0x12,
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CXL_MBOX_INVALID_SECURITY_STATE = 0x13,
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CXL_MBOX_INCORRECT_PASSPHRASE = 0x14,
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CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15,
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CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16,
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CXL_MBOX_MAX = 0x17
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} ret_code;
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struct cxl_cmd;
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typedef ret_code (*opcode_handler)(struct cxl_cmd *cmd,
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CXLDeviceState *cxl_dstate, uint16_t *len);
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struct cxl_cmd {
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const char *name;
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opcode_handler handler;
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ssize_t in;
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uint16_t effect; /* Reported in CEL */
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uint8_t *payload;
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};
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#define DEFINE_MAILBOX_HANDLER_ZEROED(name, size) \
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uint16_t __zero##name = size; \
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static ret_code cmd_##name(struct cxl_cmd *cmd, \
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CXLDeviceState *cxl_dstate, uint16_t *len) \
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{ \
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*len = __zero##name; \
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memset(cmd->payload, 0, *len); \
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return CXL_MBOX_SUCCESS; \
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}
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#define DEFINE_MAILBOX_HANDLER_NOP(name) \
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static ret_code cmd_##name(struct cxl_cmd *cmd, \
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CXLDeviceState *cxl_dstate, uint16_t *len) \
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{ \
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return CXL_MBOX_SUCCESS; \
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}
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static QemuUUID cel_uuid;
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static struct cxl_cmd cxl_cmd_set[256][256] = {};
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void cxl_process_mailbox(CXLDeviceState *cxl_dstate)
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{
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uint16_t ret = CXL_MBOX_SUCCESS;
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struct cxl_cmd *cxl_cmd;
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uint64_t status_reg;
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opcode_handler h;
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uint64_t command_reg = cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD];
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uint8_t set = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET);
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uint8_t cmd = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND);
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uint16_t len = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH);
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cxl_cmd = &cxl_cmd_set[set][cmd];
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h = cxl_cmd->handler;
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if (h) {
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if (len == cxl_cmd->in) {
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cxl_cmd->payload = cxl_dstate->mbox_reg_state +
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A_CXL_DEV_CMD_PAYLOAD;
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ret = (*h)(cxl_cmd, cxl_dstate, &len);
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assert(len <= cxl_dstate->payload_size);
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} else {
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ret = CXL_MBOX_INVALID_PAYLOAD_LENGTH;
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}
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} else {
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qemu_log_mask(LOG_UNIMP, "Command %04xh not implemented\n",
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set << 8 | cmd);
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ret = CXL_MBOX_UNSUPPORTED;
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}
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/* Set the return code */
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status_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_STS, ERRNO, ret);
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/* Set the return length */
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command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET, 0);
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command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND, 0);
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command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH, len);
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cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD] = command_reg;
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cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_STS] = status_reg;
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/* Tell the host we're done */
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ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL,
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DOORBELL, 0);
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}
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int cxl_initialize_mailbox(CXLDeviceState *cxl_dstate)
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{
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/* CXL 2.0: Table 169 Get Supported Logs Log Entry */
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const char *cel_uuidstr = "0da9c0b5-bf41-4b78-8f79-96b1623b3f17";
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for (int set = 0; set < 256; set++) {
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for (int cmd = 0; cmd < 256; cmd++) {
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if (cxl_cmd_set[set][cmd].handler) {
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struct cxl_cmd *c = &cxl_cmd_set[set][cmd];
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struct cel_log *log =
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&cxl_dstate->cel_log[cxl_dstate->cel_size];
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log->opcode = (set << 8) | cmd;
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log->effect = c->effect;
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cxl_dstate->cel_size++;
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}
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}
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}
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return qemu_uuid_parse(cel_uuidstr, &cel_uuid);
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}
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@ -2,4 +2,5 @@ softmmu_ss.add(when: 'CONFIG_CXL',
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if_true: files(
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'cxl-component-utils.c',
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'cxl-device-utils.c',
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'cxl-mailbox-utils.c',
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))
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@ -14,4 +14,7 @@
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#include "cxl_component.h"
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#include "cxl_device.h"
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#define CXL_COMPONENT_REG_BAR_IDX 0
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#define CXL_DEVICE_REG_BAR_IDX 2
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#endif
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@ -90,7 +90,21 @@ typedef struct cxl_device_state {
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};
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/* mmio for the mailbox registers 8.2.8.4 */
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MemoryRegion mailbox;
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struct {
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MemoryRegion mailbox;
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uint16_t payload_size;
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union {
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uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH];
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uint16_t mbox_reg_state16[CXL_MAILBOX_REGISTERS_LENGTH / 2];
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uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH / 4];
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uint64_t mbox_reg_state64[CXL_MAILBOX_REGISTERS_LENGTH / 8];
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};
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struct cel_log {
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uint16_t opcode;
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uint16_t effect;
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} cel_log[1 << 16];
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size_t cel_size;
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};
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/* memory region for persistent memory, HDM */
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uint64_t pmem_size;
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@ -140,6 +154,9 @@ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE_STATUS, CXL_DEVICE_CAP_HDR1_OFFSET)
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CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \
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CXL_DEVICE_CAP_REG_SIZE)
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int cxl_initialize_mailbox(CXLDeviceState *cxl_dstate);
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void cxl_process_mailbox(CXLDeviceState *cxl_dstate);
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#define cxl_device_cap_init(dstate, reg, cap_id) \
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do { \
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uint32_t *cap_hdrs = dstate->caps_reg_state32; \
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