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hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block 

Support SSE variants like the SSE-300 with an ARMSSE_CPU_PWRCTRL register
block. Because this block is per-CPU and does not clash with any of the
SSE-200 devices, we handle it with a has_cpu_pwrctrl flag like the
existing has_cachectrl, has_cpusectrl and has_cpuid, rather than
trying to add per-CPU-device support to the devinfo array handling code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-35-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-02-19 14:46:07 +00:00
parent f11de23158
commit 4668b441cb
2 changed files with 29 additions and 0 deletions
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26
hw/arm/armsse.c
View File

@ -66,6 +66,7 @@ struct ARMSSEInfo {
bool has_cachectrl;
bool has_cpusecctrl;
bool has_cpuid;
bool has_cpu_pwrctrl;
bool has_sse_counter;
Property *props;
const ARMSSEDeviceInfo *devinfo;
@ -364,6 +365,7 @@ static const ARMSSEInfo armsse_variants[] = {
.has_cachectrl = false,
.has_cpusecctrl = false,
.has_cpuid = false,
.has_cpu_pwrctrl = false,
.has_sse_counter = false,
.props = iotkit_properties,
.devinfo = iotkit_devices,
@ -381,6 +383,7 @@ static const ARMSSEInfo armsse_variants[] = {
.has_cachectrl = true,
.has_cpusecctrl = true,
.has_cpuid = true,
.has_cpu_pwrctrl = false,
.has_sse_counter = false,
.props = armsse_properties,
.devinfo = sse200_devices,
@ -660,6 +663,15 @@ static void armsse_init(Object *obj)
g_free(name);
}
}
if (info->has_cpu_pwrctrl) {
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("cpu_pwrctrl%d", i);
object_initialize_child(obj, name, &s->cpu_pwrctrl[i],
TYPE_ARMSSE_CPU_PWRCTRL);
g_free(name);
}
}
if (info->has_sse_counter) {
object_initialize_child(obj, "sse-counter", &s->sse_counter,
TYPE_SSE_COUNTER);
@ -1255,6 +1267,8 @@ static void armsse_realize(DeviceState *dev, Error **errp)
* 0x50010000: L1 icache control registers
* 0x50011000: CPUSECCTRL (CPU local security control registers)
* 0x4001f000 and 0x5001f000: CPU_IDENTITY register block
* The SSE-300 has an extra:
* 0x40012000 and 0x50012000: CPU_PWRCTRL register block
*/
if (info->has_cachectrl) {
for (i = 0; i < info->num_cpus; i++) {
@ -1301,6 +1315,18 @@ static void armsse_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr);
}
}
if (info->has_cpu_pwrctrl) {
for (i = 0; i < info->num_cpus; i++) {
MemoryRegion *mr;
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), errp)) {
return;
}
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), 0);
memory_region_add_subregion(&s->cpu_container[i], 0x40012000, mr);
}
}
if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) {
return;

3
include/hw/arm/armsse.h
View File

@ -104,6 +104,7 @@
#include "hw/misc/iotkit-sysinfo.h"
#include "hw/misc/armsse-cpuid.h"
#include "hw/misc/armsse-mhu.h"
#include "hw/misc/armsse-cpu-pwrctrl.h"
#include "hw/misc/unimp.h"
#include "hw/or-irq.h"
#include "hw/clock.h"
@ -179,6 +180,8 @@ struct ARMSSE {
ARMSSECPUID cpuid[SSE_MAX_CPUS];
ARMSSECPUPwrCtrl cpu_pwrctrl[SSE_MAX_CPUS];
/*
* 'container' holds all devices seen by all CPUs.
* 'cpu_container[i]' is the view that CPU i has: this has the