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target/hppa: Fix unit carry conditions

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Split do_unit_cond to do_unit_zero_cond to only handle conditions
versus zero.  These are the only ones that are legal for UXOR.
Simplify trans_uxor accordingly.

Rename do_unit to do_unit_addsub, since xor has been split.
Properly compute carry-out bits for add and subtract, mirroring
the code in do_add and do_sub.

Tested-by: Helge Deller <deller@gmx.de>
Reviewed-by: Helge Deller <deller@gmx.de>
Fixes: b2167459ae ("target-hppa: Implement basic arithmetic")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-03-24 15:59:37 -10:00
parent ababac165b
commit 46bb3d467c
1 changed files with 113 additions and 105 deletions
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218
target/hppa/translate.c
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@ -936,98 +936,44 @@ static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d,
return do_log_cond(ctx, c * 2 + f, d, res); return do_log_cond(ctx, c * 2 + f, d, res);
} }
/* Similar, but for unit conditions. */ /* Similar, but for unit zero conditions. */
static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res)
static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res,
TCGv_i64 in1, TCGv_i64 in2)
{ {
DisasCond cond; TCGv_i64 tmp;
TCGv_i64 tmp, cb = NULL;
uint64_t d_repl = d ? 0x0000000100000001ull : 1; uint64_t d_repl = d ? 0x0000000100000001ull : 1;
uint64_t ones = 0, sgns = 0;
if (cf & 8) {
/* Since we want to test lots of carry-out bits all at once, do not
* do our normal thing and compute carry-in of bit B+1 since that
* leaves us with carry bits spread across two words.
*/
cb = tcg_temp_new_i64();
tmp = tcg_temp_new_i64();
tcg_gen_or_i64(cb, in1, in2);
tcg_gen_and_i64(tmp, in1, in2);
tcg_gen_andc_i64(cb, cb, res);
tcg_gen_or_i64(cb, cb, tmp);
}
switch (cf >> 1) { switch (cf >> 1) {
case 0: /* never / TR */
cond = cond_make_f();
break;
case 1: /* SBW / NBW */ case 1: /* SBW / NBW */
if (d) { if (d) {
tmp = tcg_temp_new_i64(); ones = d_repl;
tcg_gen_subi_i64(tmp, res, d_repl * 0x00000001u); sgns = d_repl << 31;
tcg_gen_andc_i64(tmp, tmp, res);
tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80000000u);
cond = cond_make_0(TCG_COND_NE, tmp);
} else {
/* undefined */
cond = cond_make_f();
} }
break; break;
case 2: /* SBZ / NBZ */ case 2: /* SBZ / NBZ */
/* See hasless(v,1) from ones = d_repl * 0x01010101u;
* https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord sgns = ones << 7;
*/
tmp = tcg_temp_new_i64();
tcg_gen_subi_i64(tmp, res, d_repl * 0x01010101u);
tcg_gen_andc_i64(tmp, tmp, res);
tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80808080u);
cond = cond_make_0(TCG_COND_NE, tmp);
break; break;
case 3: /* SHZ / NHZ */ case 3: /* SHZ / NHZ */
tmp = tcg_temp_new_i64(); ones = d_repl * 0x00010001u;
tcg_gen_subi_i64(tmp, res, d_repl * 0x00010001u); sgns = ones << 15;
tcg_gen_andc_i64(tmp, tmp, res);
tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80008000u);
cond = cond_make_0(TCG_COND_NE, tmp);
break; break;
case 4: /* SDC / NDC */
tcg_gen_andi_i64(cb, cb, d_repl * 0x88888888u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
case 5: /* SWC / NWC */
if (d) {
tcg_gen_andi_i64(cb, cb, d_repl * 0x80000000u);
cond = cond_make_0(TCG_COND_NE, cb);
} else {
/* undefined */
cond = cond_make_f();
}
break;
case 6: /* SBC / NBC */
tcg_gen_andi_i64(cb, cb, d_repl * 0x80808080u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
case 7: /* SHC / NHC */
tcg_gen_andi_i64(cb, cb, d_repl * 0x80008000u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
default:
g_assert_not_reached();
} }
if (cf & 1) { if (ones == 0) {
cond.c = tcg_invert_cond(cond.c); /* Undefined, or 0/1 (never/always). */
return cf & 1 ? cond_make_t() : cond_make_f();
} }
return cond; /*
* See hasless(v,1) from
* https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
*/
tmp = tcg_temp_new_i64();
tcg_gen_subi_i64(tmp, res, ones);
tcg_gen_andc_i64(tmp, tmp, res);
tcg_gen_andi_i64(tmp, tmp, sgns);
return cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp);
} }
static TCGv_i64 get_carry(DisasContext *ctx, bool d, static TCGv_i64 get_carry(DisasContext *ctx, bool d,
@ -1330,34 +1276,86 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a,
return nullify_end(ctx); return nullify_end(ctx);
} }
static void do_unit(DisasContext *ctx, unsigned rt, TCGv_i64 in1, static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
TCGv_i64 in2, unsigned cf, bool d, bool is_tc, TCGv_i64 in2, unsigned cf, bool d,
void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64)) bool is_tc, bool is_add)
{ {
TCGv_i64 dest; TCGv_i64 dest = tcg_temp_new_i64();
uint64_t test_cb = 0;
DisasCond cond; DisasCond cond;
if (cf == 0) { /* Select which carry-out bits to test. */
dest = dest_gpr(ctx, rt); switch (cf >> 1) {
fn(dest, in1, in2); case 4: /* NDC / SDC -- 4-bit carries */
save_gpr(ctx, rt, dest); test_cb = dup_const(MO_8, 0x88);
cond_free(&ctx->null_cond); break;
} else { case 5: /* NWC / SWC -- 32-bit carries */
dest = tcg_temp_new_i64(); if (d) {
fn(dest, in1, in2); test_cb = dup_const(MO_32, INT32_MIN);
} else {
cond = do_unit_cond(cf, d, dest, in1, in2); cf &= 1; /* undefined -- map to never/always */
if (is_tc) {
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(tcg_env, tmp);
} }
save_gpr(ctx, rt, dest); break;
case 6: /* NBC / SBC -- 8-bit carries */
cond_free(&ctx->null_cond); test_cb = dup_const(MO_8, INT8_MIN);
ctx->null_cond = cond; break;
case 7: /* NHC / SHC -- 16-bit carries */
test_cb = dup_const(MO_16, INT16_MIN);
break;
} }
if (!d) {
test_cb = (uint32_t)test_cb;
}
if (!test_cb) {
/* No need to compute carries if we don't need to test them. */
if (is_add) {
tcg_gen_add_i64(dest, in1, in2);
} else {
tcg_gen_sub_i64(dest, in1, in2);
}
cond = do_unit_zero_cond(cf, d, dest);
} else {
TCGv_i64 cb = tcg_temp_new_i64();
if (d) {
TCGv_i64 cb_msb = tcg_temp_new_i64();
if (is_add) {
tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero);
tcg_gen_xor_i64(cb, in1, in2);
} else {
/* See do_sub, !is_b. */
TCGv_i64 one = tcg_constant_i64(1);
tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, ctx->zero);
tcg_gen_eqv_i64(cb, in1, in2);
}
tcg_gen_xor_i64(cb, cb, dest);
tcg_gen_extract2_i64(cb, cb, cb_msb, 1);
} else {
if (is_add) {
tcg_gen_add_i64(dest, in1, in2);
tcg_gen_xor_i64(cb, in1, in2);
} else {
tcg_gen_sub_i64(dest, in1, in2);
tcg_gen_eqv_i64(cb, in1, in2);
}
tcg_gen_xor_i64(cb, cb, dest);
tcg_gen_shri_i64(cb, cb, 1);
}
tcg_gen_andi_i64(cb, cb, test_cb);
cond = cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb);
}
if (is_tc) {
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(tcg_env, tmp);
}
save_gpr(ctx, rt, dest);
cond_free(&ctx->null_cond);
ctx->null_cond = cond;
} }
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -2748,14 +2746,24 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a)
static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a)
{ {
TCGv_i64 tcg_r1, tcg_r2; TCGv_i64 tcg_r1, tcg_r2, dest;
if (a->cf) { if (a->cf) {
nullify_over(ctx); nullify_over(ctx);
} }
tcg_r1 = load_gpr(ctx, a->r1); tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2); tcg_r2 = load_gpr(ctx, a->r2);
do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_i64); dest = dest_gpr(ctx, a->t);
tcg_gen_xor_i64(dest, tcg_r1, tcg_r2);
save_gpr(ctx, a->t, dest);
cond_free(&ctx->null_cond);
if (a->cf) {
ctx->null_cond = do_unit_zero_cond(a->cf, a->d, dest);
}
return nullify_end(ctx); return nullify_end(ctx);
} }
@ -2790,7 +2798,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc)
tcg_r2 = load_gpr(ctx, a->r2); tcg_r2 = load_gpr(ctx, a->r2);
tmp = tcg_temp_new_i64(); tmp = tcg_temp_new_i64();
tcg_gen_not_i64(tmp, tcg_r2); tcg_gen_not_i64(tmp, tcg_r2);
do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_i64); do_unit_addsub(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, true);
return nullify_end(ctx); return nullify_end(ctx);
} }
@ -2817,8 +2825,8 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i)
} }
tcg_gen_andi_i64(tmp, tmp, (uint64_t)0x1111111111111111ull); tcg_gen_andi_i64(tmp, tmp, (uint64_t)0x1111111111111111ull);
tcg_gen_muli_i64(tmp, tmp, 6); tcg_gen_muli_i64(tmp, tmp, 6);
do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false, do_unit_addsub(ctx, a->t, load_gpr(ctx, a->r), tmp,
is_i ? tcg_gen_add_i64 : tcg_gen_sub_i64); a->cf, a->d, false, is_i);
return nullify_end(ctx); return nullify_end(ctx);
} }