target/arm: Move some system registers into a substructure
Create struct ARMISARegisters, to be accessed during translation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181016223115.24100-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
202ccb6bab
commit
47576b94af
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@ -1055,17 +1055,17 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
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case 0xd5c: /* MMFR3. */
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return cpu->id_mmfr3;
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case 0xd60: /* ISAR0. */
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return cpu->id_isar0;
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return cpu->isar.id_isar0;
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case 0xd64: /* ISAR1. */
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return cpu->id_isar1;
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return cpu->isar.id_isar1;
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case 0xd68: /* ISAR2. */
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return cpu->id_isar2;
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return cpu->isar.id_isar2;
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case 0xd6c: /* ISAR3. */
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return cpu->id_isar3;
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return cpu->isar.id_isar3;
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case 0xd70: /* ISAR4. */
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return cpu->id_isar4;
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return cpu->isar.id_isar4;
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case 0xd74: /* ISAR5. */
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return cpu->id_isar5;
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return cpu->isar.id_isar5;
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case 0xd78: /* CLIDR */
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return cpu->clidr;
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case 0xd7c: /* CTR */
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178
target/arm/cpu.c
178
target/arm/cpu.c
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@ -144,9 +144,9 @@ static void arm_cpu_reset(CPUState *s)
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g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
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env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
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env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
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cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
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s->halted = cpu->start_powered_off;
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@ -938,7 +938,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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* registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
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*/
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cpu->id_pfr1 &= ~0xf0;
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cpu->id_aa64pfr0 &= ~0xf000;
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cpu->isar.id_aa64pfr0 &= ~0xf000;
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}
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if (!cpu->has_el2) {
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@ -955,7 +955,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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* registers if we don't have EL2. These are id_pfr1[15:12] and
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* id_aa64pfr0_el1[11:8].
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*/
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cpu->id_aa64pfr0 &= ~0xf00;
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cpu->isar.id_aa64pfr0 &= ~0xf00;
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cpu->id_pfr1 &= ~0xf000;
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}
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@ -1151,8 +1151,8 @@ static void arm1136_r2_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
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cpu->midr = 0x4107b362;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->isar.mvfr0 = 0x11111111;
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cpu->isar.mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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@ -1162,11 +1162,11 @@ static void arm1136_r2_initfn(Object *obj)
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->id_isar0 = 0x00140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->isar.id_isar0 = 0x00140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231111;
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cpu->isar.id_isar3 = 0x01102131;
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cpu->isar.id_isar4 = 0x141;
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cpu->reset_auxcr = 7;
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}
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@ -1183,8 +1183,8 @@ static void arm1136_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
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cpu->midr = 0x4117b363;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->isar.mvfr0 = 0x11111111;
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cpu->isar.mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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@ -1194,11 +1194,11 @@ static void arm1136_initfn(Object *obj)
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->id_isar0 = 0x00140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->isar.id_isar0 = 0x00140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231111;
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cpu->isar.id_isar3 = 0x01102131;
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cpu->isar.id_isar4 = 0x141;
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cpu->reset_auxcr = 7;
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}
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@ -1216,8 +1216,8 @@ static void arm1176_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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cpu->midr = 0x410fb767;
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cpu->reset_fpsid = 0x410120b5;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->isar.mvfr0 = 0x11111111;
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cpu->isar.mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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@ -1227,11 +1227,11 @@ static void arm1176_initfn(Object *obj)
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222100;
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cpu->id_isar0 = 0x0140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231121;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x01141;
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cpu->isar.id_isar0 = 0x0140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231121;
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cpu->isar.id_isar3 = 0x01102131;
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cpu->isar.id_isar4 = 0x01141;
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cpu->reset_auxcr = 7;
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}
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@ -1247,8 +1247,8 @@ static void arm11mpcore_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
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cpu->midr = 0x410fb022;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->isar.mvfr0 = 0x11111111;
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cpu->isar.mvfr1 = 0x00000000;
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cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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@ -1257,11 +1257,11 @@ static void arm11mpcore_initfn(Object *obj)
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cpu->id_mmfr0 = 0x01100103;
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cpu->id_mmfr1 = 0x10020302;
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cpu->id_mmfr2 = 0x01222000;
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cpu->id_isar0 = 0x00100011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11221011;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->isar.id_isar0 = 0x00100011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11221011;
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cpu->isar.id_isar3 = 0x01102131;
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cpu->isar.id_isar4 = 0x141;
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cpu->reset_auxcr = 1;
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}
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@ -1290,13 +1290,13 @@ static void cortex_m3_initfn(Object *obj)
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x00000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->id_isar0 = 0x01141110;
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cpu->id_isar1 = 0x02111000;
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cpu->id_isar2 = 0x21112231;
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cpu->id_isar3 = 0x01111110;
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cpu->id_isar4 = 0x01310102;
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cpu->id_isar5 = 0x00000000;
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cpu->id_isar6 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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cpu->isar.id_isar3 = 0x01111110;
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cpu->isar.id_isar4 = 0x01310102;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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}
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static void cortex_m4_initfn(Object *obj)
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@ -1317,13 +1317,13 @@ static void cortex_m4_initfn(Object *obj)
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x00000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->id_isar0 = 0x01141110;
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cpu->id_isar1 = 0x02111000;
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cpu->id_isar2 = 0x21112231;
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cpu->id_isar3 = 0x01111110;
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cpu->id_isar4 = 0x01310102;
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cpu->id_isar5 = 0x00000000;
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cpu->id_isar6 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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cpu->isar.id_isar3 = 0x01111110;
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cpu->isar.id_isar4 = 0x01310102;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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}
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static void cortex_m33_initfn(Object *obj)
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@ -1346,13 +1346,13 @@ static void cortex_m33_initfn(Object *obj)
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->id_isar0 = 0x01101110;
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cpu->id_isar1 = 0x02212000;
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cpu->id_isar2 = 0x20232232;
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cpu->id_isar3 = 0x01111131;
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cpu->id_isar4 = 0x01310132;
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cpu->id_isar5 = 0x00000000;
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cpu->id_isar6 = 0x00000000;
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cpu->isar.id_isar0 = 0x01101110;
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cpu->isar.id_isar1 = 0x02212000;
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cpu->isar.id_isar2 = 0x20232232;
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cpu->isar.id_isar3 = 0x01111131;
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cpu->isar.id_isar4 = 0x01310132;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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cpu->clidr = 0x00000000;
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cpu->ctr = 0x8000c000;
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}
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@ -1397,13 +1397,13 @@ static void cortex_r5_initfn(Object *obj)
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01200000;
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cpu->id_mmfr3 = 0x0211;
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cpu->id_isar0 = 0x02101111;
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cpu->id_isar1 = 0x13112111;
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cpu->id_isar2 = 0x21232141;
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cpu->id_isar3 = 0x01112131;
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cpu->id_isar4 = 0x0010142;
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cpu->id_isar5 = 0x0;
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cpu->id_isar6 = 0x0;
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cpu->isar.id_isar0 = 0x02101111;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232141;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x0010142;
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cpu->isar.id_isar5 = 0x0;
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cpu->isar.id_isar6 = 0x0;
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cpu->mp_is_up = true;
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cpu->pmsav7_dregion = 16;
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define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
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@ -1438,8 +1438,8 @@ static void cortex_a8_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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cpu->midr = 0x410fc080;
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cpu->reset_fpsid = 0x410330c0;
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cpu->mvfr0 = 0x11110222;
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cpu->mvfr1 = 0x00011111;
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cpu->isar.mvfr0 = 0x11110222;
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cpu->isar.mvfr1 = 0x00011111;
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cpu->ctr = 0x82048004;
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x1031;
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@ -1450,11 +1450,11 @@ static void cortex_a8_initfn(Object *obj)
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01202000;
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cpu->id_mmfr3 = 0x11;
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cpu->id_isar0 = 0x00101111;
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cpu->id_isar1 = 0x12112111;
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cpu->id_isar2 = 0x21232031;
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cpu->id_isar3 = 0x11112131;
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cpu->id_isar4 = 0x00111142;
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cpu->isar.id_isar0 = 0x00101111;
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cpu->isar.id_isar1 = 0x12112111;
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cpu->isar.id_isar2 = 0x21232031;
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cpu->isar.id_isar3 = 0x11112131;
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cpu->isar.id_isar4 = 0x00111142;
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cpu->dbgdidr = 0x15141000;
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cpu->clidr = (1 << 27) | (2 << 24) | 3;
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cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
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@ -1512,8 +1512,8 @@ static void cortex_a9_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_CBAR);
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cpu->midr = 0x410fc090;
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cpu->reset_fpsid = 0x41033090;
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cpu->mvfr0 = 0x11110222;
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cpu->mvfr1 = 0x01111111;
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cpu->isar.mvfr0 = 0x11110222;
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cpu->isar.mvfr1 = 0x01111111;
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cpu->ctr = 0x80038003;
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x1031;
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@ -1524,11 +1524,11 @@ static void cortex_a9_initfn(Object *obj)
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01230000;
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cpu->id_mmfr3 = 0x00002111;
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cpu->id_isar0 = 0x00101111;
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cpu->id_isar1 = 0x13112111;
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cpu->id_isar2 = 0x21232041;
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cpu->id_isar3 = 0x11112131;
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cpu->id_isar4 = 0x00111142;
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cpu->isar.id_isar0 = 0x00101111;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232041;
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cpu->isar.id_isar3 = 0x11112131;
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cpu->isar.id_isar4 = 0x00111142;
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cpu->dbgdidr = 0x35141000;
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cpu->clidr = (1 << 27) | (1 << 24) | 3;
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cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
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@ -1573,8 +1573,8 @@ static void cortex_a7_initfn(Object *obj)
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
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cpu->midr = 0x410fc075;
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cpu->reset_fpsid = 0x41023075;
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cpu->mvfr0 = 0x10110222;
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cpu->mvfr1 = 0x11111111;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x11111111;
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cpu->ctr = 0x84448003;
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x00001131;
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@ -1590,11 +1590,11 @@ static void cortex_a7_initfn(Object *obj)
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/* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
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* table 4-41 gives 0x02101110, which includes the arm div insns.
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*/
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cpu->id_isar0 = 0x02101110;
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cpu->id_isar1 = 0x13112111;
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cpu->id_isar2 = 0x21232041;
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cpu->id_isar3 = 0x11112131;
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cpu->id_isar4 = 0x10011142;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232041;
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cpu->isar.id_isar3 = 0x11112131;
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cpu->isar.id_isar4 = 0x10011142;
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cpu->dbgdidr = 0x3515f005;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
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|
|
@ -1619,8 +1619,8 @@ static void cortex_a15_initfn(Object *obj)
|
|||
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
|
||||
cpu->midr = 0x412fc0f1;
|
||||
cpu->reset_fpsid = 0x410430f0;
|
||||
cpu->mvfr0 = 0x10110222;
|
||||
cpu->mvfr1 = 0x11111111;
|
||||
cpu->isar.mvfr0 = 0x10110222;
|
||||
cpu->isar.mvfr1 = 0x11111111;
|
||||
cpu->ctr = 0x8444c004;
|
||||
cpu->reset_sctlr = 0x00c50078;
|
||||
cpu->id_pfr0 = 0x00001131;
|
||||
|
|
@ -1633,11 +1633,11 @@ static void cortex_a15_initfn(Object *obj)
|
|||
cpu->id_mmfr1 = 0x20000000;
|
||||
cpu->id_mmfr2 = 0x01240000;
|
||||
cpu->id_mmfr3 = 0x02102211;
|
||||
cpu->id_isar0 = 0x02101110;
|
||||
cpu->id_isar1 = 0x13112111;
|
||||
cpu->id_isar2 = 0x21232041;
|
||||
cpu->id_isar3 = 0x11112131;
|
||||
cpu->id_isar4 = 0x10011142;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232041;
|
||||
cpu->isar.id_isar3 = 0x11112131;
|
||||
cpu->isar.id_isar4 = 0x10011142;
|
||||
cpu->dbgdidr = 0x3515f021;
|
||||
cpu->clidr = 0x0a200023;
|
||||
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
|
||||
|
|
|
|||
|
|
@ -795,13 +795,28 @@ struct ARMCPU {
|
|||
* ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
|
||||
* is used for reset values of non-constant registers; no reset_
|
||||
* prefix means a constant register.
|
||||
* Some of these registers are split out into a substructure that
|
||||
* is shared with the translators to control the ISA.
|
||||
*/
|
||||
struct ARMISARegisters {
|
||||
uint32_t id_isar0;
|
||||
uint32_t id_isar1;
|
||||
uint32_t id_isar2;
|
||||
uint32_t id_isar3;
|
||||
uint32_t id_isar4;
|
||||
uint32_t id_isar5;
|
||||
uint32_t id_isar6;
|
||||
uint32_t mvfr0;
|
||||
uint32_t mvfr1;
|
||||
uint32_t mvfr2;
|
||||
uint64_t id_aa64isar0;
|
||||
uint64_t id_aa64isar1;
|
||||
uint64_t id_aa64pfr0;
|
||||
uint64_t id_aa64pfr1;
|
||||
} isar;
|
||||
uint32_t midr;
|
||||
uint32_t revidr;
|
||||
uint32_t reset_fpsid;
|
||||
uint32_t mvfr0;
|
||||
uint32_t mvfr1;
|
||||
uint32_t mvfr2;
|
||||
uint32_t ctr;
|
||||
uint32_t reset_sctlr;
|
||||
uint32_t id_pfr0;
|
||||
|
|
@ -815,21 +830,10 @@ struct ARMCPU {
|
|||
uint32_t id_mmfr2;
|
||||
uint32_t id_mmfr3;
|
||||
uint32_t id_mmfr4;
|
||||
uint32_t id_isar0;
|
||||
uint32_t id_isar1;
|
||||
uint32_t id_isar2;
|
||||
uint32_t id_isar3;
|
||||
uint32_t id_isar4;
|
||||
uint32_t id_isar5;
|
||||
uint32_t id_isar6;
|
||||
uint64_t id_aa64pfr0;
|
||||
uint64_t id_aa64pfr1;
|
||||
uint64_t id_aa64dfr0;
|
||||
uint64_t id_aa64dfr1;
|
||||
uint64_t id_aa64afr0;
|
||||
uint64_t id_aa64afr1;
|
||||
uint64_t id_aa64isar0;
|
||||
uint64_t id_aa64isar1;
|
||||
uint64_t id_aa64mmfr0;
|
||||
uint64_t id_aa64mmfr1;
|
||||
uint32_t dbgdidr;
|
||||
|
|
|
|||
|
|
@ -121,9 +121,9 @@ static void aarch64_a57_initfn(Object *obj)
|
|||
cpu->midr = 0x411fd070;
|
||||
cpu->revidr = 0x00000000;
|
||||
cpu->reset_fpsid = 0x41034070;
|
||||
cpu->mvfr0 = 0x10110222;
|
||||
cpu->mvfr1 = 0x12111111;
|
||||
cpu->mvfr2 = 0x00000043;
|
||||
cpu->isar.mvfr0 = 0x10110222;
|
||||
cpu->isar.mvfr1 = 0x12111111;
|
||||
cpu->isar.mvfr2 = 0x00000043;
|
||||
cpu->ctr = 0x8444c004;
|
||||
cpu->reset_sctlr = 0x00c50838;
|
||||
cpu->id_pfr0 = 0x00000131;
|
||||
|
|
@ -134,18 +134,18 @@ static void aarch64_a57_initfn(Object *obj)
|
|||
cpu->id_mmfr1 = 0x40000000;
|
||||
cpu->id_mmfr2 = 0x01260000;
|
||||
cpu->id_mmfr3 = 0x02102211;
|
||||
cpu->id_isar0 = 0x02101110;
|
||||
cpu->id_isar1 = 0x13112111;
|
||||
cpu->id_isar2 = 0x21232042;
|
||||
cpu->id_isar3 = 0x01112131;
|
||||
cpu->id_isar4 = 0x00011142;
|
||||
cpu->id_isar5 = 0x00011121;
|
||||
cpu->id_isar6 = 0;
|
||||
cpu->id_aa64pfr0 = 0x00002222;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232042;
|
||||
cpu->isar.id_isar3 = 0x01112131;
|
||||
cpu->isar.id_isar4 = 0x00011142;
|
||||
cpu->isar.id_isar5 = 0x00011121;
|
||||
cpu->isar.id_isar6 = 0;
|
||||
cpu->isar.id_aa64pfr0 = 0x00002222;
|
||||
cpu->id_aa64dfr0 = 0x10305106;
|
||||
cpu->pmceid0 = 0x00000000;
|
||||
cpu->pmceid1 = 0x00000000;
|
||||
cpu->id_aa64isar0 = 0x00011120;
|
||||
cpu->isar.id_aa64isar0 = 0x00011120;
|
||||
cpu->id_aa64mmfr0 = 0x00001124;
|
||||
cpu->dbgdidr = 0x3516d000;
|
||||
cpu->clidr = 0x0a200023;
|
||||
|
|
@ -182,9 +182,9 @@ static void aarch64_a53_initfn(Object *obj)
|
|||
cpu->midr = 0x410fd034;
|
||||
cpu->revidr = 0x00000000;
|
||||
cpu->reset_fpsid = 0x41034070;
|
||||
cpu->mvfr0 = 0x10110222;
|
||||
cpu->mvfr1 = 0x12111111;
|
||||
cpu->mvfr2 = 0x00000043;
|
||||
cpu->isar.mvfr0 = 0x10110222;
|
||||
cpu->isar.mvfr1 = 0x12111111;
|
||||
cpu->isar.mvfr2 = 0x00000043;
|
||||
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
|
||||
cpu->reset_sctlr = 0x00c50838;
|
||||
cpu->id_pfr0 = 0x00000131;
|
||||
|
|
@ -195,16 +195,16 @@ static void aarch64_a53_initfn(Object *obj)
|
|||
cpu->id_mmfr1 = 0x40000000;
|
||||
cpu->id_mmfr2 = 0x01260000;
|
||||
cpu->id_mmfr3 = 0x02102211;
|
||||
cpu->id_isar0 = 0x02101110;
|
||||
cpu->id_isar1 = 0x13112111;
|
||||
cpu->id_isar2 = 0x21232042;
|
||||
cpu->id_isar3 = 0x01112131;
|
||||
cpu->id_isar4 = 0x00011142;
|
||||
cpu->id_isar5 = 0x00011121;
|
||||
cpu->id_isar6 = 0;
|
||||
cpu->id_aa64pfr0 = 0x00002222;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232042;
|
||||
cpu->isar.id_isar3 = 0x01112131;
|
||||
cpu->isar.id_isar4 = 0x00011142;
|
||||
cpu->isar.id_isar5 = 0x00011121;
|
||||
cpu->isar.id_isar6 = 0;
|
||||
cpu->isar.id_aa64pfr0 = 0x00002222;
|
||||
cpu->id_aa64dfr0 = 0x10305106;
|
||||
cpu->id_aa64isar0 = 0x00011120;
|
||||
cpu->isar.id_aa64isar0 = 0x00011120;
|
||||
cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
|
||||
cpu->dbgdidr = 0x3516d000;
|
||||
cpu->clidr = 0x0a200023;
|
||||
|
|
@ -240,9 +240,9 @@ static void aarch64_a72_initfn(Object *obj)
|
|||
cpu->midr = 0x410fd083;
|
||||
cpu->revidr = 0x00000000;
|
||||
cpu->reset_fpsid = 0x41034080;
|
||||
cpu->mvfr0 = 0x10110222;
|
||||
cpu->mvfr1 = 0x12111111;
|
||||
cpu->mvfr2 = 0x00000043;
|
||||
cpu->isar.mvfr0 = 0x10110222;
|
||||
cpu->isar.mvfr1 = 0x12111111;
|
||||
cpu->isar.mvfr2 = 0x00000043;
|
||||
cpu->ctr = 0x8444c004;
|
||||
cpu->reset_sctlr = 0x00c50838;
|
||||
cpu->id_pfr0 = 0x00000131;
|
||||
|
|
@ -253,17 +253,17 @@ static void aarch64_a72_initfn(Object *obj)
|
|||
cpu->id_mmfr1 = 0x40000000;
|
||||
cpu->id_mmfr2 = 0x01260000;
|
||||
cpu->id_mmfr3 = 0x02102211;
|
||||
cpu->id_isar0 = 0x02101110;
|
||||
cpu->id_isar1 = 0x13112111;
|
||||
cpu->id_isar2 = 0x21232042;
|
||||
cpu->id_isar3 = 0x01112131;
|
||||
cpu->id_isar4 = 0x00011142;
|
||||
cpu->id_isar5 = 0x00011121;
|
||||
cpu->id_aa64pfr0 = 0x00002222;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232042;
|
||||
cpu->isar.id_isar3 = 0x01112131;
|
||||
cpu->isar.id_isar4 = 0x00011142;
|
||||
cpu->isar.id_isar5 = 0x00011121;
|
||||
cpu->isar.id_aa64pfr0 = 0x00002222;
|
||||
cpu->id_aa64dfr0 = 0x10305106;
|
||||
cpu->pmceid0 = 0x00000000;
|
||||
cpu->pmceid1 = 0x00000000;
|
||||
cpu->id_aa64isar0 = 0x00011120;
|
||||
cpu->isar.id_aa64isar0 = 0x00011120;
|
||||
cpu->id_aa64mmfr0 = 0x00001124;
|
||||
cpu->dbgdidr = 0x3516d000;
|
||||
cpu->clidr = 0x0a200023;
|
||||
|
|
|
|||
|
|
@ -4873,7 +4873,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
|
|||
static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
|
||||
{
|
||||
ARMCPU *cpu = arm_env_get_cpu(env);
|
||||
uint64_t pfr0 = cpu->id_aa64pfr0;
|
||||
uint64_t pfr0 = cpu->isar.id_aa64pfr0;
|
||||
|
||||
if (env->gicv3state) {
|
||||
pfr0 |= 1 << 24;
|
||||
|
|
@ -4940,27 +4940,27 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->id_isar0 },
|
||||
.resetvalue = cpu->isar.id_isar0 },
|
||||
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->id_isar1 },
|
||||
.resetvalue = cpu->isar.id_isar1 },
|
||||
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->id_isar2 },
|
||||
.resetvalue = cpu->isar.id_isar2 },
|
||||
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->id_isar3 },
|
||||
.resetvalue = cpu->isar.id_isar3 },
|
||||
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->id_isar4 },
|
||||
.resetvalue = cpu->isar.id_isar4 },
|
||||
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->id_isar5 },
|
||||
.resetvalue = cpu->isar.id_isar5 },
|
||||
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
|
|
@ -4968,7 +4968,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->id_isar6 },
|
||||
.resetvalue = cpu->isar.id_isar6 },
|
||||
REGINFO_SENTINEL
|
||||
};
|
||||
define_arm_cp_regs(cpu, v6_idregs);
|
||||
|
|
@ -5039,7 +5039,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->id_aa64pfr1},
|
||||
.resetvalue = cpu->isar.id_aa64pfr1},
|
||||
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
|
|
@ -5100,11 +5100,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->id_aa64isar0 },
|
||||
.resetvalue = cpu->isar.id_aa64isar0 },
|
||||
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->id_aa64isar1 },
|
||||
.resetvalue = cpu->isar.id_aa64isar1 },
|
||||
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
|
|
@ -5164,15 +5164,15 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->mvfr0 },
|
||||
.resetvalue = cpu->isar.mvfr0 },
|
||||
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->mvfr1 },
|
||||
.resetvalue = cpu->isar.mvfr1 },
|
||||
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.resetvalue = cpu->mvfr2 },
|
||||
.resetvalue = cpu->isar.mvfr2 },
|
||||
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
|
|
|
|||
Loading…
Reference in New Issue