From 477023a6038e8f457c604b138198f76d093b9a87 Mon Sep 17 00:00:00 2001 From: j_mayer Date: Sun, 30 Sep 2007 01:01:08 +0000 Subject: [PATCH] Improve single-precision floats load & stores: as the PowerPC registers only store double-precision floats, use float64_to_float32 & float32_to_float64 to do the appropriate conversion. Implement stfiwx. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3280 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-ppc/op_mem.h | 67 ++++++++++++++++++++++++++++++++------- target-ppc/translate.c | 72 +++++++++++++++++++----------------------- 2 files changed, 87 insertions(+), 52 deletions(-) diff --git a/target-ppc/op_mem.h b/target-ppc/op_mem.h index 13440817bf..71dfb1e347 100644 --- a/target-ppc/op_mem.h +++ b/target-ppc/op_mem.h @@ -403,11 +403,30 @@ void OPPROTO glue(glue(glue(op_st, name), _64), MEMSUFFIX) (void) \ } #endif +static inline void glue(stfs, MEMSUFFIX) (target_ulong EA, double d) +{ + glue(stfl, MEMSUFFIX)(EA, float64_to_float32(d, &env->fp_status)); +} + +static inline void glue(stfiwx, MEMSUFFIX) (target_ulong EA, double d) +{ + union { + double d; + uint64_t u; + } u; + + /* Store the low order 32 bits without any conversion */ + u.d = d; + glue(stl, MEMSUFFIX)(EA, u.u); +} + PPC_STF_OP(fd, stfq); -PPC_STF_OP(fs, stfl); +PPC_STF_OP(fs, stfs); +PPC_STF_OP(fiwx, stfiwx); #if defined(TARGET_PPC64) PPC_STF_OP_64(fd, stfq); -PPC_STF_OP_64(fs, stfl); +PPC_STF_OP_64(fs, stfs); +PPC_STF_OP_64(fiwx, stfiwx); #endif static inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d) @@ -429,14 +448,14 @@ static inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d) glue(stfq, MEMSUFFIX)(EA, u.d); } -static inline void glue(stflr, MEMSUFFIX) (target_ulong EA, float f) +static inline void glue(stfsr, MEMSUFFIX) (target_ulong EA, double d) { union { float f; uint32_t u; } u; - u.f = f; + u.f = float64_to_float32(d, &env->fp_status); u.u = ((u.u & 0xFF000000UL) >> 24) | ((u.u & 0x00FF0000ULL) >> 8) | ((u.u & 0x0000FF00UL) << 8) | @@ -444,11 +463,30 @@ static inline void glue(stflr, MEMSUFFIX) (target_ulong EA, float f) glue(stfl, MEMSUFFIX)(EA, u.f); } +static inline void glue(stfiwxr, MEMSUFFIX) (target_ulong EA, double d) +{ + union { + double d; + uint64_t u; + } u; + + /* Store the low order 32 bits without any conversion */ + u.d = d; + u.u = ((u.u & 0xFF000000UL) >> 24) | + ((u.u & 0x00FF0000ULL) >> 8) | + ((u.u & 0x0000FF00UL) << 8) | + ((u.u & 0x000000FFULL) << 24); + glue(stl, MEMSUFFIX)(EA, u.u); +} + + PPC_STF_OP(fd_le, stfqr); -PPC_STF_OP(fs_le, stflr); +PPC_STF_OP(fs_le, stfsr); +PPC_STF_OP(fiwx_le, stfiwxr); #if defined(TARGET_PPC64) PPC_STF_OP_64(fd_le, stfqr); -PPC_STF_OP_64(fs_le, stflr); +PPC_STF_OP_64(fs_le, stfsr); +PPC_STF_OP_64(fiwx_le, stfiwxr); #endif /*** Floating-point load ***/ @@ -468,11 +506,16 @@ void OPPROTO glue(glue(glue(op_l, name), _64), MEMSUFFIX) (void) \ } #endif +static inline double glue(ldfs, MEMSUFFIX) (target_ulong EA) +{ + return float32_to_float64(glue(ldfl, MEMSUFFIX)(EA), &env->fp_status); +} + PPC_LDF_OP(fd, ldfq); -PPC_LDF_OP(fs, ldfl); +PPC_LDF_OP(fs, ldfs); #if defined(TARGET_PPC64) PPC_LDF_OP_64(fd, ldfq); -PPC_LDF_OP_64(fs, ldfl); +PPC_LDF_OP_64(fs, ldfs); #endif static inline double glue(ldfqr, MEMSUFFIX) (target_ulong EA) @@ -495,7 +538,7 @@ static inline double glue(ldfqr, MEMSUFFIX) (target_ulong EA) return u.d; } -static inline float glue(ldflr, MEMSUFFIX) (target_ulong EA) +static inline double glue(ldfsr, MEMSUFFIX) (target_ulong EA) { union { float f; @@ -508,14 +551,14 @@ static inline float glue(ldflr, MEMSUFFIX) (target_ulong EA) ((u.u & 0x0000FF00UL) << 8) | ((u.u & 0x000000FFULL) << 24); - return u.f; + return float32_to_float64(u.f, &env->fp_status); } PPC_LDF_OP(fd_le, ldfqr); -PPC_LDF_OP(fs_le, ldflr); +PPC_LDF_OP(fs_le, ldfsr); #if defined(TARGET_PPC64) PPC_LDF_OP_64(fd_le, ldfqr); -PPC_LDF_OP_64(fs_le, ldflr); +PPC_LDF_OP_64(fs_le, ldfsr); #endif /* Load and set reservation */ diff --git a/target-ppc/translate.c b/target-ppc/translate.c index e88cfafaee..7f84ed7d69 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2581,8 +2581,8 @@ GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03CF0801, PPC_MEM_SYNC) } /*** Floating-point load ***/ -#define GEN_LDF(width, opc) \ -GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \ +#define GEN_LDF(width, opc, type) \ +GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \ { \ if (unlikely(!ctx->fpu_enabled)) { \ GEN_EXCP_NO_FP(ctx); \ @@ -2593,8 +2593,8 @@ GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \ gen_op_store_FT0_fpr(rD(ctx->opcode)); \ } -#define GEN_LDUF(width, opc) \ -GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \ +#define GEN_LDUF(width, opc, type) \ +GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ { \ if (unlikely(!ctx->fpu_enabled)) { \ GEN_EXCP_NO_FP(ctx); \ @@ -2610,8 +2610,8 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \ gen_op_store_T0_gpr(rA(ctx->opcode)); \ } -#define GEN_LDUXF(width, opc) \ -GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \ +#define GEN_LDUXF(width, opc, type) \ +GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ { \ if (unlikely(!ctx->fpu_enabled)) { \ GEN_EXCP_NO_FP(ctx); \ @@ -2627,8 +2627,8 @@ GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \ gen_op_store_T0_gpr(rA(ctx->opcode)); \ } -#define GEN_LDXF(width, opc2, opc3) \ -GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \ +#define GEN_LDXF(width, opc2, opc3, type) \ +GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ { \ if (unlikely(!ctx->fpu_enabled)) { \ GEN_EXCP_NO_FP(ctx); \ @@ -2639,21 +2639,21 @@ GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \ gen_op_store_FT0_fpr(rD(ctx->opcode)); \ } -#define GEN_LDFS(width, op) \ +#define GEN_LDFS(width, op, type) \ OP_LD_TABLE(width); \ -GEN_LDF(width, op | 0x20); \ -GEN_LDUF(width, op | 0x21); \ -GEN_LDUXF(width, op | 0x01); \ -GEN_LDXF(width, 0x17, op | 0x00) +GEN_LDF(width, op | 0x20, type); \ +GEN_LDUF(width, op | 0x21, type); \ +GEN_LDUXF(width, op | 0x01, type); \ +GEN_LDXF(width, 0x17, op | 0x00, type) /* lfd lfdu lfdux lfdx */ -GEN_LDFS(fd, 0x12); +GEN_LDFS(fd, 0x12, PPC_FLOAT); /* lfs lfsu lfsux lfsx */ -GEN_LDFS(fs, 0x10); +GEN_LDFS(fs, 0x10, PPC_FLOAT); /*** Floating-point store ***/ -#define GEN_STF(width, opc) \ -GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \ +#define GEN_STF(width, opc, type) \ +GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ { \ if (unlikely(!ctx->fpu_enabled)) { \ GEN_EXCP_NO_FP(ctx); \ @@ -2664,8 +2664,8 @@ GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \ op_ldst(st##width); \ } -#define GEN_STUF(width, opc) \ -GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \ +#define GEN_STUF(width, opc, type) \ +GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ { \ if (unlikely(!ctx->fpu_enabled)) { \ GEN_EXCP_NO_FP(ctx); \ @@ -2681,8 +2681,8 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \ gen_op_store_T0_gpr(rA(ctx->opcode)); \ } -#define GEN_STUXF(width, opc) \ -GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \ +#define GEN_STUXF(width, opc, type) \ +GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ { \ if (unlikely(!ctx->fpu_enabled)) { \ GEN_EXCP_NO_FP(ctx); \ @@ -2698,8 +2698,8 @@ GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \ gen_op_store_T0_gpr(rA(ctx->opcode)); \ } -#define GEN_STXF(width, opc2, opc3) \ -GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \ +#define GEN_STXF(width, opc2, opc3, type) \ +GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ { \ if (unlikely(!ctx->fpu_enabled)) { \ GEN_EXCP_NO_FP(ctx); \ @@ -2710,30 +2710,22 @@ GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \ op_ldst(st##width); \ } -#define GEN_STFS(width, op) \ +#define GEN_STFS(width, op, type) \ OP_ST_TABLE(width); \ -GEN_STF(width, op | 0x20); \ -GEN_STUF(width, op | 0x21); \ -GEN_STUXF(width, op | 0x01); \ -GEN_STXF(width, 0x17, op | 0x00) +GEN_STF(width, op | 0x20, type); \ +GEN_STUF(width, op | 0x21, type); \ +GEN_STUXF(width, op | 0x01, type); \ +GEN_STXF(width, 0x17, op | 0x00, type) /* stfd stfdu stfdux stfdx */ -GEN_STFS(fd, 0x16); +GEN_STFS(fd, 0x16, PPC_FLOAT); /* stfs stfsu stfsux stfsx */ -GEN_STFS(fs, 0x14); +GEN_STFS(fs, 0x14, PPC_FLOAT); /* Optional: */ /* stfiwx */ -GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT_STFIWX) -{ - if (unlikely(!ctx->fpu_enabled)) { - GEN_EXCP_NO_FP(ctx); - return; - } - gen_addr_reg_index(ctx); - /* XXX: TODO: memcpy low order 32 bits of FRP(rs) into memory */ - GEN_EXCP_INVAL(ctx); -} +OP_ST_TABLE(fiwx); +GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX); /*** Branch ***/ static inline void gen_goto_tb (DisasContext *ctx, int n, target_ulong dest)