tcg: initial ia64 support
A few words about design choices: * On IA64, instructions should be grouped by bundle, and dependencies between instructions declared. A first version of this code tried to schedule instructions automatically, but was very complex and too invasive for the current common TCG code (ops not ending at instruction boundaries, code retranslation breaking already generated code, etc.) It was also not very efficient, as dependencies between TCG ops is not available. Instead the option taken by the current implementation does not try to fill the bundle by scheduling instructions, but by providing ops not available as an ia64 instruction, and by offering 22-bit constant loading for most of the instructions. With both options the bundle are filled at approximately the same level. * Up to 128 registers can be affected to a function on IA64, but TCG limits this number to 64, which is actually more than enough. The register affectation is the following: - r0: used to map a constant argument with value 0 - r1: global pointer - r2, r3: internal use - r4 to r6: not used to avoid saving them - r7: env structure - r8 to r11: free for TCG (call clobbered) - r12: stack pointer - r13: thread pointer - r14 to r31: free for TCG (call clobbered) - r32: reserved (return address) - r33: reserved (PFS) - r33 to r63: free for TCG * The IA64 architecture has only 64-bit registers and no 32-bit instructions (the only exception being cmp4). Therefore 64-bit registers and instructions are used for 32-bit ops. The adopted strategy is the same as the ABI, that is the higher 32 bits are undefined. Most ops (and, or, add, shl, etc.) can directly use the 64-bit registers, while some others have to sign-extend (sar, div, etc.) or zero-extend (shr, divu, etc.) the register first. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno
parent
ebf50fb3b9
commit
477ba62001
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@ -193,6 +193,8 @@ elif check_define _ARCH_PPC ; then
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fi
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elif check_define __mips__ ; then
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cpu="mips"
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elif check_define __ia64__ ; then
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cpu="ia64"
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else
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cpu=`uname -m`
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fi
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@ -717,6 +719,9 @@ case "$cpu" in
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mips*)
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host_guest_base="yes"
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;;
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ia64*)
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host_guest_base="yes"
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;;
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esac
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[ -z "$guest_base" ] && guest_base="$host_guest_base"
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@ -2698,9 +2703,6 @@ alpha)
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# Ensure there's only a single GP
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cflags="-msmall-data $cflags"
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;;
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ia64)
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cflags="-mno-sdata $cflags"
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;;
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esac
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if test "$target_softmmu" = "yes" ; then
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@ -2745,21 +2747,11 @@ if test "$target_linux_user" = "yes" -o "$target_bsd_user" = "yes" ; then
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# -static is used to avoid g1/g3 usage by the dynamic linker
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ldflags="$linker_script -static $ldflags"
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;;
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ia64)
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ldflags="-Wl,-G0 $linker_script -static $ldflags"
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;;
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i386|x86_64|ppc|ppc64|s390|sparc64|alpha|arm|m68k|mips|mips64)
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i386|x86_64|ppc|ppc64|s390|sparc64|alpha|arm|m68k|mips|mips64|ia64)
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ldflags="$linker_script $ldflags"
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;;
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esac
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fi
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if test "$target_softmmu" = "yes" ; then
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case "$ARCH" in
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ia64)
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ldflags="-Wl,-G0 $linker_script -static $ldflags"
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;;
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esac
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fi
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echo "LDFLAGS+=$ldflags" >> $config_target_mak
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echo "QEMU_CFLAGS+=$cflags" >> $config_target_mak
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@ -3,7 +3,7 @@
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/* CPU interfaces that are target indpendent. */
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#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__)
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#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
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#define WORDS_ALIGNED
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#endif
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,156 @@
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
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* Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#define TCG_TARGET_IA64 1
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#define TCG_TARGET_REG_BITS 64
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/* We only map the first 64 registers */
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#define TCG_TARGET_NB_REGS 64
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enum {
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TCG_REG_R0 = 0,
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TCG_REG_R1,
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TCG_REG_R2,
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TCG_REG_R3,
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TCG_REG_R4,
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_R15,
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TCG_REG_R16,
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TCG_REG_R17,
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TCG_REG_R18,
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TCG_REG_R19,
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TCG_REG_R20,
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TCG_REG_R21,
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TCG_REG_R22,
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TCG_REG_R23,
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TCG_REG_R24,
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TCG_REG_R25,
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TCG_REG_R26,
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TCG_REG_R27,
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TCG_REG_R28,
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TCG_REG_R29,
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TCG_REG_R30,
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TCG_REG_R31,
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TCG_REG_R32,
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TCG_REG_R33,
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TCG_REG_R34,
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TCG_REG_R35,
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TCG_REG_R36,
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TCG_REG_R37,
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TCG_REG_R38,
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TCG_REG_R39,
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TCG_REG_R40,
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TCG_REG_R41,
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TCG_REG_R42,
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TCG_REG_R43,
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TCG_REG_R44,
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TCG_REG_R45,
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TCG_REG_R46,
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TCG_REG_R47,
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TCG_REG_R48,
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TCG_REG_R49,
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TCG_REG_R50,
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TCG_REG_R51,
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TCG_REG_R52,
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TCG_REG_R53,
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TCG_REG_R54,
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TCG_REG_R55,
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TCG_REG_R56,
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TCG_REG_R57,
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TCG_REG_R58,
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TCG_REG_R59,
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TCG_REG_R60,
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TCG_REG_R61,
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TCG_REG_R62,
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TCG_REG_R63,
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};
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#define TCG_CT_CONST_ZERO 0x100
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#define TCG_CT_CONST_S22 0x200
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_R12
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#define TCG_TARGET_STACK_ALIGN 16
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#define TCG_TARGET_CALL_STACK_OFFSET 16
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/* optional instructions */
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#define TCG_TARGET_HAS_andc_i32
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#define TCG_TARGET_HAS_andc_i64
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#define TCG_TARGET_HAS_bswap16_i32
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#define TCG_TARGET_HAS_bswap16_i64
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#define TCG_TARGET_HAS_bswap32_i32
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#define TCG_TARGET_HAS_bswap32_i64
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#define TCG_TARGET_HAS_bswap64_i64
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#define TCG_TARGET_HAS_eqv_i32
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#define TCG_TARGET_HAS_eqv_i64
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#define TCG_TARGET_HAS_ext8s_i32
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#define TCG_TARGET_HAS_ext16s_i32
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#define TCG_TARGET_HAS_ext8s_i64
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#define TCG_TARGET_HAS_ext16s_i64
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#define TCG_TARGET_HAS_ext32s_i64
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#define TCG_TARGET_HAS_ext8u_i32
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#define TCG_TARGET_HAS_ext16u_i32
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#define TCG_TARGET_HAS_ext8u_i64
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#define TCG_TARGET_HAS_ext16u_i64
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#define TCG_TARGET_HAS_ext32u_i64
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#define TCG_TARGET_HAS_nand_i32
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#define TCG_TARGET_HAS_nand_i64
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#define TCG_TARGET_HAS_nor_i32
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#define TCG_TARGET_HAS_nor_i64
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#define TCG_TARGET_HAS_orc_i32
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#define TCG_TARGET_HAS_orc_i64
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#define TCG_TARGET_HAS_rot_i32
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#define TCG_TARGET_HAS_rot_i64
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/* optional instructions automatically implemented */
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#undef TCG_TARGET_HAS_neg_i32 /* sub r1, r0, r3 */
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#undef TCG_TARGET_HAS_neg_i64 /* sub r1, r0, r3 */
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#undef TCG_TARGET_HAS_not_i32 /* xor r1, -1, r3 */
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#undef TCG_TARGET_HAS_not_i64 /* xor r1, -1, r3 */
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/* Note: must be synced with dyngen-exec.h */
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#define TCG_AREG0 TCG_REG_R7
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/* Guest base is supported */
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#define TCG_TARGET_HAS_GUEST_BASE
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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start = start & ~(32UL - 1UL);
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stop = (stop + (32UL - 1UL)) & ~(32UL - 1UL);
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for (; start < stop; start += 32UL) {
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asm volatile ("fc.i %0" :: "r" (start));
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}
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asm volatile (";;sync.i;;srlz.i;;");
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}
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