OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

arm, cocoa and misc: 

* MAINTAINERS file updates
  * Mark remaining global TypeInfo instances as const
  * checkpatch: Ensure that TypeInfos are const
  * arm hvf: Handle unknown ID registers as RES0
  * Make KVM -cpu max exactly like -cpu host
  * Fix '-cpu max' for HVF
  * Support PAuth extension for hvf
  * Kconfig: Add I2C_DEVICES device group
  * Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c bus
  * hw/arm/armv7m: Handle disconnected clock inputs
  * osdep.h: pull out various things into new header files
  * hw/timer: fix a9gtimer vmstate
  * hw/arm: add initial mori-bmc board
  * ui/cocoa: Remove allowedFileTypes restriction in SavePanel
  * ui/cocoa: Do not alert even without block devices
  * ui/cocoa: Fix the leak of qemu_console_get_label
 -----BEGIN PGP SIGNATURE-----
 
 iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmITlAUZHHBldGVyLm1h
 eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vL3D/9GHh2rsgTqld+hnQVDWd6F
 zCAFz2598QDuGOzwiTORR2pAkgDcPbOzYG79HbqC9tuDmEPQ/fCdUq33wlWbI0s4
 AzVfQwIq7ILbLk+BDxTmZz6sG0lrnabL8hQAbBW/vM18HI5mSvOqjDJUx/vlAeTH
 txZmlW4i3vd4EmB/FQy9cTNW1SzYFu4c5IManJpdNxL3Fuhm7BYOqsQ44Fqjf0ho
 UFEHvJGQQlXhaknXEtvdv8dGm5CJ0J8ceDA0DBZOuzOtXpPKKvVsTfTzcehKSkT+
 vd9POq9z7Qk1pC4yXb3CHtX1glB4/iM83DYNYnfnvwmnek6YnjIReTl0skN92BzS
 HwOmEJHdneW1gmZb8WYyMZG9KfDGq6+0R7luQDAT7GqHI0v5qpAVUhSpykbHKKbb
 wmlBUOr5NtISQHOMTUsLwgYEwvq8UNF+wjQbaelST7VFNCzTfPDg01r0pKFfpGOr
 OCPcDPxNVOv4TsOScfd0ill65fy92OPS3QIjyUCKS+1xGeMR1Lv8LW2VxOI2msNm
 w684scJ73YKPfBK5T8NLZTmhYm+Mu4BYBkxCbyaoiVLrw/Zwt/3sgfnh7+oPR/j6
 LTVOLA2qudm6zez5lZNh1ulDjyI/pLLr+dnbTbHO6stkbHYNirRIEyuQ0ho3oXoH
 h9Ci/W62hnydR0N9m93fNA==
 =pLon
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220221-1' into staging

arm, cocoa and misc:
 * MAINTAINERS file updates
 * Mark remaining global TypeInfo instances as const
 * checkpatch: Ensure that TypeInfos are const
 * arm hvf: Handle unknown ID registers as RES0
 * Make KVM -cpu max exactly like -cpu host
 * Fix '-cpu max' for HVF
 * Support PAuth extension for hvf
 * Kconfig: Add I2C_DEVICES device group
 * Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c bus
 * hw/arm/armv7m: Handle disconnected clock inputs
 * osdep.h: pull out various things into new header files
 * hw/timer: fix a9gtimer vmstate
 * hw/arm: add initial mori-bmc board
 * ui/cocoa: Remove allowedFileTypes restriction in SavePanel
 * ui/cocoa: Do not alert even without block devices
 * ui/cocoa: Fix the leak of qemu_console_get_label

# gpg: Signature made Mon 21 Feb 2022 13:30:45 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20220221-1: (25 commits)
  ui/cocoa: Fix the leak of qemu_console_get_label
  ui/cocoa: Do not alert even without block devices
  ui/cocoa: Remove allowedFileTypes restriction in SavePanel
  hw/arm: add initial mori-bmc board
  hw/timer: fix a9gtimer vmstate
  MAINTAINERS: Add Akihiko Odaki to macOS-relateds
  include: Move hardware version declarations to new qemu/hw-version.h
  include: Move qemu_[id]cache_* declarations to new qemu/cacheinfo.h
  include: Move QEMU_MAP_* constants to mmap-alloc.h
  include: Move qemu_mprotect_*() to new qemu/mprotect.h
  include: Move qemu_madvise() and related #defines to new qemu/madvise.h
  hw/arm/armv7m: Handle disconnected clock inputs
  Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c bus
  Kconfig: Add I2C_DEVICES device group
  target/arm: Support PAuth extension for hvf
  target/arm: Fix '-cpu max' for HVF
  target/arm: Unindent unnecessary else-clause
  target/arm: Make KVM -cpu max exactly like -cpu host
  target/arm: Use aarch64_cpu_register() for 'host' CPU type
  target/arm: Move '-cpu host' code to cpu64.c
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-02-21 13:32:25 +00:00
parent e670f6d825 ca51160492
commit 477c3b934a
84 changed files with 606 additions and 393 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
MAINTAINERS
View File

@ -2189,6 +2189,7 @@ F: tests/qtest/prom-env-test.c
VM Generation ID
S: Orphan
R: Ani Sinha <ani@anisinha.ca>
F: hw/acpi/vmgenid.c
F: include/hw/acpi/vmgenid.h
F: docs/specs/vmgenid.txt
@ -2204,6 +2205,7 @@ F: hw/misc/led.c
Unimplemented device
M: Peter Maydell <peter.maydell@linaro.org>
R: Philippe Mathieu-Daudé <f4bug@amsat.org>
R: Ani Sinha <ani@anisinha.ca>
S: Maintained
F: include/hw/misc/unimp.h
F: hw/misc/unimp.c
@ -2211,6 +2213,7 @@ F: hw/misc/unimp.c
Empty slot
M: Artyom Tarasenko <atar4qemu@gmail.com>
R: Philippe Mathieu-Daudé <f4bug@amsat.org>
R: Ani Sinha <ani@anisinha.ca>
S: Maintained
F: include/hw/misc/empty_slot.h
F: hw/misc/empty_slot.c
@ -2413,6 +2416,7 @@ F: audio/alsaaudio.c
Core Audio framework backend
M: Gerd Hoffmann <kraxel@redhat.com>
R: Christian Schoenebeck <qemu_oss@crudebyte.com>
R: Akihiko Odaki <akihiko.odaki@gmail.com>
S: Odd Fixes
F: audio/coreaudio.c
@ -2665,6 +2669,7 @@ F: util/drm.c
Cocoa graphics
M: Peter Maydell <peter.maydell@linaro.org>
R: Akihiko Odaki <akihiko.odaki@gmail.com>
S: Odd Fixes
F: ui/cocoa.m

1
accel/tcg/translate-all.c
View File

@ -51,6 +51,7 @@
#include "qemu/qemu-print.h"
#include "qemu/timer.h"
#include "qemu/main-loop.h"
#include "qemu/cacheinfo.h"
#include "exec/log.h"
#include "sysemu/cpus.h"
#include "sysemu/cpu-timers.h"

1
backends/hostmem-file.c
View File

@ -14,6 +14,7 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qemu/madvise.h"
#include "sysemu/hostmem.h"
#include "qom/object_interfaces.h"
#include "qom/object.h"

1
backends/hostmem.c
View File

@ -19,6 +19,7 @@
#include "qemu/config-file.h"
#include "qom/object_interfaces.h"
#include "qemu/mmap-alloc.h"
#include "qemu/madvise.h"
#ifdef CONFIG_NUMA
#include <numaif.h>

8
docs/devel/kconfig.rst
View File

@ -192,11 +192,15 @@ declares its dependencies in different ways:
no directive and are not used in the Makefile either; they only appear
as conditions for ``default y`` directives.
QEMU currently has two device groups, ``PCI_DEVICES`` and
``TEST_DEVICES``. PCI devices usually have a ``default y if
QEMU currently has three device groups, ``PCI_DEVICES``, ``I2C_DEVICES``,
and ``TEST_DEVICES``. PCI devices usually have a ``default y if
PCI_DEVICES`` directive rather than just ``default y``. This lets
some boards (notably s390) easily support a subset of PCI devices,
for example only VFIO (passthrough) and virtio-pci devices.
``I2C_DEVICES`` is similar to ``PCI_DEVICES``. It contains i2c devices
that users might reasonably want to plug in to an i2c bus on any
board (and not ones which are very board-specific or that need
to be wired up in a way that can't be done on the command line).
``TEST_DEVICES`` instead is used for devices that are rarely used on
production virtual machines, but provide useful hooks to test QEMU
or KVM.

1
docs/system/arm/nuvoton.rst
View File

@ -21,6 +21,7 @@ Hyperscale applications. The following machines are based on this chip :
- ``quanta-gbs-bmc`` Quanta GBS server BMC
- ``quanta-gsj`` Quanta GSJ server BMC
- ``kudo-bmc`` Fii USA Kudo server BMC
- ``mori-bmc`` Fii USA Mori server BMC
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
variants of NPCM750 and NPCM730, respectively. These are currently not

10
hw/arm/Kconfig
View File

@ -46,6 +46,7 @@ config DIGIC
config EXYNOS4
bool
imply I2C_DEVICES
select A9MPCORE
select I2C
select LAN9118
@ -184,6 +185,7 @@ config REALVIEW
bool
imply PCI_DEVICES
imply PCI_TESTDEV
imply I2C_DEVICES
select SMC91C111
select LAN9118
select A9MPCORE
@ -229,6 +231,7 @@ config SABRELITE
config STELLARIS
bool
imply I2C_DEVICES
select ARM_V7M
select CMSDK_APB_WATCHDOG
select I2C
@ -406,6 +409,7 @@ config NPCM7XX
config FSL_IMX25
bool
imply I2C_DEVICES
select IMX
select IMX_FEC
select IMX_I2C
@ -414,6 +418,7 @@ config FSL_IMX25
config FSL_IMX31
bool
imply I2C_DEVICES
select SERIAL
select IMX
select IMX_I2C
@ -422,6 +427,7 @@ config FSL_IMX31
config FSL_IMX6
bool
imply I2C_DEVICES
select A9MPCORE
select IMX
select IMX_FEC
@ -450,6 +456,7 @@ config ASPEED_SOC
config MPS2
bool
imply I2C_DEVICES
select ARMSSE
select LAN9118
select MPS2_FPGAIO
@ -466,6 +473,7 @@ config FSL_IMX7
bool
imply PCI_DEVICES
imply TEST_DEVICES
imply I2C_DEVICES
select A15MPCORE
select PCI
select IMX
@ -481,6 +489,7 @@ config ARM_SMMUV3
config FSL_IMX6UL
bool
imply I2C_DEVICES
select A15MPCORE
select IMX
select IMX_FEC
@ -495,6 +504,7 @@ config MICROBIT
config NRF51_SOC
bool
imply I2C_DEVICES
select I2C
select ARM_V7M
select UNIMP

26
hw/arm/armv7m.c
View File

@ -284,6 +284,12 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
return;
}
/* cpuclk must be connected; refclk is optional */
if (!clock_has_source(s->cpuclk)) {
error_setg(errp, "armv7m: cpuclk must be connected");
return;
}
memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
s->cpu = ARM_CPU(object_new_with_props(s->cpu_type, OBJECT(s), "cpu",
@ -420,8 +426,18 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
&s->sysreg_ns_mem);
}
/* Create and map the systick devices */
qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk", s->refclk);
/*
* Create and map the systick devices. Note that we only connect
* refclk if it has been connected to us; otherwise the systick
* device gets the wrong answer for clock_has_source(refclk), because
* it has an immediate source (the ARMv7M's clock object) but not
* an ultimate source, and then it won't correctly auto-select the
* CPU clock as its only possible clock source.
*/
if (clock_has_source(s->refclk)) {
qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk",
s->refclk);
}
qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
return;
@ -438,8 +454,10 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
*/
object_initialize_child(OBJECT(dev), "systick-reg-s",
&s->systick[M_REG_S], TYPE_SYSTICK);
qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk",
s->refclk);
if (clock_has_source(s->refclk)) {
qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk",
s->refclk);
}
qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "cpuclk",
s->cpuclk);

32
hw/arm/npcm7xx_boards.c
View File

@ -34,6 +34,7 @@
#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff
#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff
#define MORI_BMC_POWER_ON_STRAPS 0x00001fff
static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
@ -429,6 +430,21 @@ static void kudo_bmc_init(MachineState *machine)
npcm7xx_load_kernel(machine, soc);
}
static void mori_bmc_init(MachineState *machine)
{
NPCM7xxState *soc;
soc = npcm7xx_create_soc(machine, MORI_BMC_POWER_ON_STRAPS);
npcm7xx_connect_dram(soc, machine->ram);
qdev_realize(DEVICE(soc), NULL, &error_fatal);
npcm7xx_load_bootrom(machine, soc);
npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f",
drive_get(IF_MTD, 3, 0));
npcm7xx_load_kernel(machine, soc);
}
static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
{
NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));
@ -501,6 +517,18 @@ static void kudo_bmc_machine_class_init(ObjectClass *oc, void *data)
mc->default_ram_size = 1 * GiB;
};
static void mori_bmc_machine_class_init(ObjectClass *oc, void *data)
{
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
MachineClass *mc = MACHINE_CLASS(oc);
npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
mc->desc = "Mori BMC (Cortex-A9)";
mc->init = mori_bmc_init;
mc->default_ram_size = 1 * GiB;
}
static const TypeInfo npcm7xx_machine_types[] = {
{
.name = TYPE_NPCM7XX_MACHINE,
@ -525,6 +553,10 @@ static const TypeInfo npcm7xx_machine_types[] = {
.name = MACHINE_TYPE_NAME("kudo-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = kudo_bmc_machine_class_init,
}, {
.name = MACHINE_TYPE_NAME("mori-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = mori_bmc_machine_class_init,
},
};

1
hw/arm/nseries.c
View File

@ -24,6 +24,7 @@
#include "chardev/char.h"
#include "qemu/cutils.h"
#include "qemu/bswap.h"
#include "qemu/hw-version.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "sysemu/sysemu.h"

2
hw/core/generic-loader.c
View File

@ -207,7 +207,7 @@ static void generic_loader_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
static TypeInfo generic_loader_info = {
static const TypeInfo generic_loader_info = {
.name = TYPE_GENERIC_LOADER,
.parent = TYPE_DEVICE,
.instance_size = sizeof(GenericLoaderState),

2
hw/core/guest-loader.c
View File

@ -129,7 +129,7 @@ static void guest_loader_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
static TypeInfo guest_loader_info = {
static const TypeInfo guest_loader_info = {
.name = TYPE_GUEST_LOADER,
.parent = TYPE_DEVICE,
.instance_size = sizeof(GuestLoaderState),

2
hw/display/bcm2835_fb.c
View File

@ -454,7 +454,7 @@ static void bcm2835_fb_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2835_fb;
}
static TypeInfo bcm2835_fb_info = {
static const TypeInfo bcm2835_fb_info = {
.name = TYPE_BCM2835_FB,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BCM2835FBState),

2
hw/display/i2c-ddc.c
View File

@ -113,7 +113,7 @@ static void i2c_ddc_class_init(ObjectClass *oc, void *data)
isc->send = i2c_ddc_tx;
}
static TypeInfo i2c_ddc_info = {
static const TypeInfo i2c_ddc_info = {
.name = TYPE_I2CDDC,
.parent = TYPE_I2C_SLAVE,
.instance_size = sizeof(I2CDDCState),

4
hw/display/macfb.c
View File

@ -782,14 +782,14 @@ static void macfb_nubus_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, macfb_nubus_properties);
}
static TypeInfo macfb_sysbus_info = {
static const TypeInfo macfb_sysbus_info = {
.name = TYPE_MACFB,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MacfbSysBusState),
.class_init = macfb_sysbus_class_init,
};
static TypeInfo macfb_nubus_info = {
static const TypeInfo macfb_nubus_info = {
.name = TYPE_NUBUS_MACFB,
.parent = TYPE_NUBUS_DEVICE,
.instance_size = sizeof(MacfbNubusState),

2
hw/display/virtio-vga.c
View File

@ -220,7 +220,7 @@ static void virtio_vga_base_class_init(ObjectClass *klass, void *data)
virtio_vga_set_big_endian_fb);
}
static TypeInfo virtio_vga_base_info = {
static const TypeInfo virtio_vga_base_info = {
.name = TYPE_VIRTIO_VGA_BASE,
.parent = TYPE_VIRTIO_PCI,
.instance_size = sizeof(VirtIOVGABase),

2
hw/dma/bcm2835_dma.c
View File

@ -394,7 +394,7 @@ static void bcm2835_dma_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2835_dma;
}
static TypeInfo bcm2835_dma_info = {
static const TypeInfo bcm2835_dma_info = {
.name = TYPE_BCM2835_DMA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BCM2835DMAState),

5
hw/i2c/Kconfig
View File

@ -1,6 +1,11 @@
config I2C
bool
config I2C_DEVICES
# Device group for i2c devices which can reasonably be user-plugged
# to any board's i2c bus
bool
config SMBUS
bool
select I2C

2
hw/i386/pc_piix.c
View File

@ -867,7 +867,7 @@ static void isa_bridge_class_init(ObjectClass *klass, void *data)
k->class_id = PCI_CLASS_BRIDGE_ISA;
};
static TypeInfo isa_bridge_info = {
static const TypeInfo isa_bridge_info = {
.name = "igd-passthrough-isa-bridge",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIDevice),

2
hw/i386/sgx-epc.c
View File

@ -167,7 +167,7 @@ static void sgx_epc_class_init(ObjectClass *oc, void *data)
mdc->fill_device_info = sgx_epc_md_fill_device_info;
}
static TypeInfo sgx_epc_info = {
static const TypeInfo sgx_epc_info = {
.name = TYPE_SGX_EPC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(SGXEPCDevice),

1
hw/ide/core.c
View File

@ -29,6 +29,7 @@
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
#include "qemu/timer.h"
#include "qemu/hw-version.h"
#include "sysemu/sysemu.h"
#include "sysemu/blockdev.h"
#include "sysemu/dma.h"

2
hw/intc/bcm2835_ic.c
View File

@ -227,7 +227,7 @@ static void bcm2835_ic_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2835_ic;
}
static TypeInfo bcm2835_ic_info = {
static const TypeInfo bcm2835_ic_info = {
.name = TYPE_BCM2835_IC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BCM2835ICState),

2
hw/intc/bcm2836_control.c
View File

@ -392,7 +392,7 @@ static void bcm2836_control_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2836_control;
}
static TypeInfo bcm2836_control_info = {
static const TypeInfo bcm2836_control_info = {
.name = TYPE_BCM2836_CONTROL,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BCM2836ControlState),

4
hw/ipmi/ipmi.c
View File

@ -85,7 +85,7 @@ static void ipmi_interface_class_init(ObjectClass *class, void *data)
ik->do_hw_op = ipmi_do_hw_op;
}
static TypeInfo ipmi_interface_type_info = {
static const TypeInfo ipmi_interface_type_info = {
.name = TYPE_IPMI_INTERFACE,
.parent = TYPE_INTERFACE,
.class_size = sizeof(IPMIInterfaceClass),
@ -120,7 +120,7 @@ static void bmc_class_init(ObjectClass *oc, void *data)
device_class_set_props(dc, ipmi_bmc_properties);
}
static TypeInfo ipmi_bmc_type_info = {
static const TypeInfo ipmi_bmc_type_info = {
.name = TYPE_IPMI_BMC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(IPMIBmc),

2
hw/mem/nvdimm.c
View File

@ -264,7 +264,7 @@ static void nvdimm_class_init(ObjectClass *oc, void *data)
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
static TypeInfo nvdimm_info = {
static const TypeInfo nvdimm_info = {
.name = TYPE_NVDIMM,
.parent = TYPE_PC_DIMM,
.class_size = sizeof(NVDIMMClass),

2
hw/mem/pc-dimm.c
View File

@ -291,7 +291,7 @@ static void pc_dimm_class_init(ObjectClass *oc, void *data)
mdc->fill_device_info = pc_dimm_md_fill_device_info;
}
static TypeInfo pc_dimm_info = {
static const TypeInfo pc_dimm_info = {
.name = TYPE_PC_DIMM,
.parent = TYPE_DEVICE,
.instance_size = sizeof(PCDIMMDevice),

2
hw/misc/bcm2835_mbox.c
View File

@ -323,7 +323,7 @@ static void bcm2835_mbox_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2835_mbox;
}
static TypeInfo bcm2835_mbox_info = {
static const TypeInfo bcm2835_mbox_info = {
.name = TYPE_BCM2835_MBOX,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BCM2835MboxState),

2
hw/misc/bcm2835_powermgt.c
View File

@ -144,7 +144,7 @@ static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2835_powermgt;
}
static TypeInfo bcm2835_powermgt_info = {
static const TypeInfo bcm2835_powermgt_info = {
.name = TYPE_BCM2835_POWERMGT,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BCM2835PowerMgtState),

2
hw/misc/bcm2835_property.c
View File

@ -421,7 +421,7 @@ static void bcm2835_property_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2835_property;
}
static TypeInfo bcm2835_property_info = {
static const TypeInfo bcm2835_property_info = {
.name = TYPE_BCM2835_PROPERTY,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BCM2835PropertyState),

2
hw/misc/bcm2835_rng.c
View File

@ -131,7 +131,7 @@ static void bcm2835_rng_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2835_rng;
}
static TypeInfo bcm2835_rng_info = {
static const TypeInfo bcm2835_rng_info = {
.name = TYPE_BCM2835_RNG,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BCM2835RngState),

2
hw/misc/pvpanic-isa.c
View File

@ -77,7 +77,7 @@ static void pvpanic_isa_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
static TypeInfo pvpanic_isa_info = {
static const TypeInfo pvpanic_isa_info = {
.name = TYPE_PVPANIC_ISA_DEVICE,
.parent = TYPE_ISA_DEVICE,
.instance_size = sizeof(PVPanicISAState),

2
hw/misc/pvpanic-pci.c
View File

@ -74,7 +74,7 @@ static void pvpanic_pci_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
static TypeInfo pvpanic_pci_info = {
static const TypeInfo pvpanic_pci_info = {
.name = TYPE_PVPANIC_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PVPanicPCIState),

2
hw/net/fsl_etsec/etsec.c
View File

@ -430,7 +430,7 @@ static void etsec_class_init(ObjectClass *klass, void *data)
dc->user_creatable = true;
}
static TypeInfo etsec_info = {
static const TypeInfo etsec_info = {
.name = TYPE_ETSEC_COMMON,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(eTSEC),

2
hw/ppc/prep_systemio.c
View File

@ -300,7 +300,7 @@ static void prep_systemio_class_initfn(ObjectClass *klass, void *data)
device_class_set_props(dc, prep_systemio_properties);
}
static TypeInfo prep_systemio800_info = {
static const TypeInfo prep_systemio800_info = {
.name = TYPE_PREP_SYSTEMIO,
.parent = TYPE_ISA_DEVICE,
.instance_size = sizeof(PrepSystemIoState),

2
hw/ppc/spapr_iommu.c
View File

@ -685,7 +685,7 @@ static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
}
static TypeInfo spapr_tce_table_info = {
static const TypeInfo spapr_tce_table_info = {
.name = TYPE_SPAPR_TCE_TABLE,
.parent = TYPE_DEVICE,
.instance_size = sizeof(SpaprTceTable),

2
hw/rtc/Kconfig
View File

@ -1,10 +1,12 @@
config DS1338
bool
depends on I2C
default y if I2C_DEVICES
config M41T80
bool
depends on I2C
default y if I2C_DEVICES
config M48T59
bool

2
hw/s390x/s390-pci-bus.c
View File

@ -1392,7 +1392,7 @@ static const TypeInfo s390_pci_device_info = {
.class_init = s390_pci_device_class_init,
};
static TypeInfo s390_pci_iommu_info = {
static const TypeInfo s390_pci_iommu_info = {
.name = TYPE_S390_PCI_IOMMU,
.parent = TYPE_OBJECT,
.instance_size = sizeof(S390PCIIOMMU),

2
hw/s390x/sclp.c
View File

@ -460,7 +460,7 @@ static void sclp_class_init(ObjectClass *oc, void *data)
sc->service_interrupt = service_interrupt;
}
static TypeInfo sclp_info = {
static const TypeInfo sclp_info = {
.name = TYPE_SCLP,
.parent = TYPE_DEVICE,
.instance_init = sclp_init,

2
hw/s390x/tod-kvm.c
View File

@ -147,7 +147,7 @@ static void kvm_s390_tod_init(Object *obj)
td->stopped = false;
}
static TypeInfo kvm_s390_tod_info = {
static const TypeInfo kvm_s390_tod_info = {
.name = TYPE_KVM_S390_TOD,
.parent = TYPE_S390_TOD,
.instance_size = sizeof(S390TODState),

2
hw/s390x/tod-tcg.c
View File

@ -73,7 +73,7 @@ static void qemu_s390_tod_init(Object *obj)
}
}
static TypeInfo qemu_s390_tod_info = {
static const TypeInfo qemu_s390_tod_info = {
.name = TYPE_QEMU_S390_TOD,
.parent = TYPE_S390_TOD,
.instance_size = sizeof(S390TODState),

2
hw/s390x/tod.c
View File

@ -123,7 +123,7 @@ static void s390_tod_class_init(ObjectClass *oc, void *data)
dc->user_creatable = false;
}
static TypeInfo s390_tod_info = {
static const TypeInfo s390_tod_info = {
.name = TYPE_S390_TOD,
.parent = TYPE_DEVICE,
.instance_size = sizeof(S390TODState),

2
hw/scsi/lsi53c895a.c
View File

@ -2352,7 +2352,7 @@ static void lsi53c810_class_init(ObjectClass *klass, void *data)
k->device_id = PCI_DEVICE_ID_LSI_53C810;
}
static TypeInfo lsi53c810_info = {
static const TypeInfo lsi53c810_info = {
.name = TYPE_LSI53C810,
.parent = TYPE_LSI53C895A,
.class_init = lsi53c810_class_init,

1
hw/scsi/megasas.c
View File

@ -28,6 +28,7 @@
#include "hw/pci/msix.h"
#include "qemu/iov.h"
#include "qemu/module.h"
#include "qemu/hw-version.h"
#include "hw/scsi/scsi.h"
#include "scsi/constants.h"
#include "trace.h"

1
hw/scsi/scsi-bus.c
View File

@ -3,6 +3,7 @@
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qemu/option.h"
#include "qemu/hw-version.h"
#include "hw/qdev-properties.h"
#include "hw/scsi/scsi.h"
#include "migration/qemu-file-types.h"

1
hw/scsi/scsi-disk.c
View File

@ -25,6 +25,7 @@
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"
#include "qemu/hw-version.h"
#include "hw/scsi/scsi.h"
#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"

2
hw/sd/allwinner-sdhost.c
View File

@ -835,7 +835,7 @@ static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
sc->max_desc_size = 64 * KiB;
}
static TypeInfo allwinner_sdhost_info = {
static const TypeInfo allwinner_sdhost_info = {
.name = TYPE_AW_SDHOST,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_init = allwinner_sdhost_init,

2
hw/sd/aspeed_sdhci.c
View File

@ -198,7 +198,7 @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
device_class_set_props(dc, aspeed_sdhci_properties);
}
static TypeInfo aspeed_sdhci_info = {
static const TypeInfo aspeed_sdhci_info = {
.name = TYPE_ASPEED_SDHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AspeedSDHCIState),

2
hw/sd/bcm2835_sdhost.c
View File

@ -436,7 +436,7 @@ static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2835_sdhost;
}
static TypeInfo bcm2835_sdhost_info = {
static const TypeInfo bcm2835_sdhost_info = {
.name = TYPE_BCM2835_SDHOST,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BCM2835SDHostState),

2
hw/sd/cadence_sdhci.c
View File

@ -175,7 +175,7 @@ static void cadence_sdhci_class_init(ObjectClass *classp, void *data)
dc->vmsd = &vmstate_cadence_sdhci;
}
static TypeInfo cadence_sdhci_info = {
static const TypeInfo cadence_sdhci_info = {
.name = TYPE_CADENCE_SDHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(CadenceSDHCIState),

2
hw/sd/npcm7xx_sdhci.c
View File

@ -166,7 +166,7 @@ static void npcm7xx_sdhci_instance_init(Object *obj)
TYPE_SYSBUS_SDHCI);
}
static TypeInfo npcm7xx_sdhci_info = {
static const TypeInfo npcm7xx_sdhci_info = {
.name = TYPE_NPCM7XX_SDHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCM7xxSDHCIState),

5
hw/sensor/Kconfig
View File

@ -1,18 +1,22 @@
config TMP105
bool
depends on I2C
default y if I2C_DEVICES
config TMP421
bool
depends on I2C
default y if I2C_DEVICES
config DPS310
bool
depends on I2C
default y if I2C_DEVICES
config EMC141X
bool
depends on I2C
default y if I2C_DEVICES
config ADM1272
bool
@ -25,3 +29,4 @@ config MAX34451
config LSM303DLHC_MAG
bool
depends on I2C
default y if I2C_DEVICES

21
hw/timer/a9gtimer.c
View File

@ -318,6 +318,12 @@ static void a9_gtimer_realize(DeviceState *dev, Error **errp)
}
}
static bool vmstate_a9_gtimer_control_needed(void *opaque)
{
A9GTimerState *s = opaque;
return s->control != 0;
}
static const VMStateDescription vmstate_a9_gtimer_per_cpu = {
.name = "arm.cortex-a9-global-timer.percpu",
.version_id = 1,
@ -331,6 +337,17 @@ static const VMStateDescription vmstate_a9_gtimer_per_cpu = {
}
};
static const VMStateDescription vmstate_a9_gtimer_control = {
.name = "arm.cortex-a9-global-timer.control",
.version_id = 1,
.minimum_version_id = 1,
.needed = vmstate_a9_gtimer_control_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT32(control, A9GTimerState),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_a9_gtimer = {
.name = "arm.cortex-a9-global-timer",
.version_id = 1,
@ -344,6 +361,10 @@ static const VMStateDescription vmstate_a9_gtimer = {
1, vmstate_a9_gtimer_per_cpu,
A9GTimerPerCPU),
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription*[]) {
&vmstate_a9_gtimer_control,
NULL
}
};

2
hw/usb/dev-mtp.c
View File

@ -2106,7 +2106,7 @@ static void usb_mtp_class_initfn(ObjectClass *klass, void *data)
device_class_set_props(dc, mtp_properties);
}
static TypeInfo mtp_info = {
static const TypeInfo mtp_info = {
.name = TYPE_USB_MTP,
.parent = TYPE_USB_DEVICE,
.instance_size = sizeof(MTPState),

2
hw/usb/host-libusb.c
View File

@ -1801,7 +1801,7 @@ static void usb_host_class_initfn(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
static TypeInfo usb_host_dev_info = {
static const TypeInfo usb_host_dev_info = {
.name = TYPE_USB_HOST_DEVICE,
.parent = TYPE_USB_DEVICE,
.instance_size = sizeof(USBHostDevice),

2
hw/vfio/igd.c
View File

@ -199,7 +199,7 @@ static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass, void *data)
k->class_id = PCI_CLASS_BRIDGE_ISA;
}
static TypeInfo vfio_pci_igd_lpc_bridge_info = {
static const TypeInfo vfio_pci_igd_lpc_bridge_info = {
.name = "vfio-pci-igd-lpc-bridge",
.parent = TYPE_PCI_DEVICE,
.class_init = vfio_pci_igd_lpc_bridge_class_init,

1
hw/virtio/virtio-balloon.c
View File

@ -17,6 +17,7 @@
#include "qemu/iov.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "qemu/madvise.h"
#include "hw/virtio/virtio.h"
#include "hw/mem/pc-dimm.h"
#include "hw/qdev-properties.h"

2
hw/virtio/virtio-pmem.c
View File

@ -182,7 +182,7 @@ static void virtio_pmem_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
static TypeInfo virtio_pmem_info = {
static const TypeInfo virtio_pmem_info = {
.name = TYPE_VIRTIO_PMEM,
.parent = TYPE_VIRTIO_DEVICE,
.class_size = sizeof(VirtIOPMEMClass),

21
include/qemu/cacheinfo.h Normal file
View File

@ -0,0 +1,21 @@
/*
* QEMU host cacheinfo information
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef QEMU_CACHEINFO_H
#define QEMU_CACHEINFO_H
/*
* These variables represent our best guess at the host icache and
* dcache sizes, expressed both as the size in bytes and as the
* base-2 log of the size in bytes. They are initialized at startup
* (via an attribute 'constructor' function).
*/
extern int qemu_icache_linesize;
extern int qemu_icache_linesize_log;
extern int qemu_dcache_linesize;
extern int qemu_dcache_linesize_log;
#endif

27
include/qemu/hw-version.h Normal file
View File

@ -0,0 +1,27 @@
/*
* QEMU "hardware version" machinery
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef QEMU_HW_VERSION_H
#define QEMU_HW_VERSION_H
/*
* Starting on QEMU 2.5, qemu_hw_version() returns "2.5+" by default
* instead of QEMU_VERSION, so setting hw_version on MachineClass
* is no longer mandatory.
*
* Do NOT change this string, or it will break compatibility on all
* machine classes that don't set hw_version.
*/
#define QEMU_HW_VERSION "2.5+"
/* QEMU "hardware version" setting. Used to replace code that exposed
* QEMU_VERSION to guests in the past and need to keep compatibility.
* Do not use qemu_hw_version() in new code.
*/
void qemu_set_hw_version(const char *);
const char *qemu_hw_version(void);
#endif

95
include/qemu/madvise.h Normal file
View File

@ -0,0 +1,95 @@
/*
* QEMU madvise wrapper functions
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef QEMU_MADVISE_H
#define QEMU_MADVISE_H
#define QEMU_MADV_INVALID -1
#if defined(CONFIG_MADVISE)
#define QEMU_MADV_WILLNEED MADV_WILLNEED
#define QEMU_MADV_DONTNEED MADV_DONTNEED
#ifdef MADV_DONTFORK
#define QEMU_MADV_DONTFORK MADV_DONTFORK
#else
#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID
#endif
#ifdef MADV_MERGEABLE
#define QEMU_MADV_MERGEABLE MADV_MERGEABLE
#else
#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID
#endif
#ifdef MADV_UNMERGEABLE
#define QEMU_MADV_UNMERGEABLE MADV_UNMERGEABLE
#else
#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID
#endif
#ifdef MADV_DODUMP
#define QEMU_MADV_DODUMP MADV_DODUMP
#else
#define QEMU_MADV_DODUMP QEMU_MADV_INVALID
#endif
#ifdef MADV_DONTDUMP
#define QEMU_MADV_DONTDUMP MADV_DONTDUMP
#else
#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID
#endif
#ifdef MADV_HUGEPAGE
#define QEMU_MADV_HUGEPAGE MADV_HUGEPAGE
#else
#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID
#endif
#ifdef MADV_NOHUGEPAGE
#define QEMU_MADV_NOHUGEPAGE MADV_NOHUGEPAGE
#else
#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID
#endif
#ifdef MADV_REMOVE
#define QEMU_MADV_REMOVE MADV_REMOVE
#else
#define QEMU_MADV_REMOVE QEMU_MADV_DONTNEED
#endif
#ifdef MADV_POPULATE_WRITE
#define QEMU_MADV_POPULATE_WRITE MADV_POPULATE_WRITE
#else
#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID
#endif
#elif defined(CONFIG_POSIX_MADVISE)
#define QEMU_MADV_WILLNEED POSIX_MADV_WILLNEED
#define QEMU_MADV_DONTNEED POSIX_MADV_DONTNEED
#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID
#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID
#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID
#define QEMU_MADV_DODUMP QEMU_MADV_INVALID
#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID
#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID
#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID
#define QEMU_MADV_REMOVE QEMU_MADV_DONTNEED
#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID
#else /* no-op */
#define QEMU_MADV_WILLNEED QEMU_MADV_INVALID
#define QEMU_MADV_DONTNEED QEMU_MADV_INVALID
#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID
#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID
#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID
#define QEMU_MADV_DODUMP QEMU_MADV_INVALID
#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID
#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID
#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID
#define QEMU_MADV_REMOVE QEMU_MADV_INVALID
#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID
#endif
int qemu_madvise(void *addr, size_t len, int advice);
#endif

23
include/qemu/mmap-alloc.h
View File

@ -35,4 +35,27 @@ void *qemu_ram_mmap(int fd,
void qemu_ram_munmap(int fd, void *ptr, size_t size);
/*
* Abstraction of PROT_ and MAP_ flags as passed to mmap(), for example,
* consumed by qemu_ram_mmap().
*/
/* Map PROT_READ instead of PROT_READ | PROT_WRITE. */
#define QEMU_MAP_READONLY (1 << 0)
/* Use MAP_SHARED instead of MAP_PRIVATE. */
#define QEMU_MAP_SHARED (1 << 1)
/*
* Use MAP_SYNC | MAP_SHARED_VALIDATE if supported. Ignored without
* QEMU_MAP_SHARED. If mapping fails, warn and fallback to !QEMU_MAP_SYNC.
*/
#define QEMU_MAP_SYNC (1 << 2)
/*
* Use MAP_NORESERVE to skip reservation of swap space (or huge pages if
* applicable). Bail out if not supported/effective.
*/
#define QEMU_MAP_NORESERVE (1 << 3)
#endif

14
include/qemu/mprotect.h Normal file
View File

@ -0,0 +1,14 @@
/*
* QEMU mprotect functions
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef QEMU_MPROTECT_H
#define QEMU_MPROTECT_H
int qemu_mprotect_rw(void *addr, size_t size);
int qemu_mprotect_rwx(void *addr, size_t size);
int qemu_mprotect_none(void *addr, size_t size);
#endif

132
include/qemu/osdep.h
View File

@ -401,112 +401,6 @@ static inline void qemu_cleanup_generic_vfree(void *p)
*/
#define QEMU_AUTO_VFREE __attribute__((cleanup(qemu_cleanup_generic_vfree)))
/*
* Abstraction of PROT_ and MAP_ flags as passed to mmap(), for example,
* consumed by qemu_ram_mmap().
*/
/* Map PROT_READ instead of PROT_READ | PROT_WRITE. */
#define QEMU_MAP_READONLY (1 << 0)
/* Use MAP_SHARED instead of MAP_PRIVATE. */
#define QEMU_MAP_SHARED (1 << 1)
/*
* Use MAP_SYNC | MAP_SHARED_VALIDATE if supported. Ignored without
* QEMU_MAP_SHARED. If mapping fails, warn and fallback to !QEMU_MAP_SYNC.
*/
#define QEMU_MAP_SYNC (1 << 2)
/*
* Use MAP_NORESERVE to skip reservation of swap space (or huge pages if
* applicable). Bail out if not supported/effective.
*/
#define QEMU_MAP_NORESERVE (1 << 3)
#define QEMU_MADV_INVALID -1
#if defined(CONFIG_MADVISE)
#define QEMU_MADV_WILLNEED MADV_WILLNEED
#define QEMU_MADV_DONTNEED MADV_DONTNEED
#ifdef MADV_DONTFORK
#define QEMU_MADV_DONTFORK MADV_DONTFORK
#else
#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID
#endif
#ifdef MADV_MERGEABLE
#define QEMU_MADV_MERGEABLE MADV_MERGEABLE
#else
#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID
#endif
#ifdef MADV_UNMERGEABLE
#define QEMU_MADV_UNMERGEABLE MADV_UNMERGEABLE
#else
#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID
#endif
#ifdef MADV_DODUMP
#define QEMU_MADV_DODUMP MADV_DODUMP
#else
#define QEMU_MADV_DODUMP QEMU_MADV_INVALID
#endif
#ifdef MADV_DONTDUMP
#define QEMU_MADV_DONTDUMP MADV_DONTDUMP
#else
#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID
#endif
#ifdef MADV_HUGEPAGE
#define QEMU_MADV_HUGEPAGE MADV_HUGEPAGE
#else
#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID
#endif
#ifdef MADV_NOHUGEPAGE
#define QEMU_MADV_NOHUGEPAGE MADV_NOHUGEPAGE
#else
#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID
#endif
#ifdef MADV_REMOVE
#define QEMU_MADV_REMOVE MADV_REMOVE
#else
#define QEMU_MADV_REMOVE QEMU_MADV_DONTNEED
#endif
#ifdef MADV_POPULATE_WRITE
#define QEMU_MADV_POPULATE_WRITE MADV_POPULATE_WRITE
#else
#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID
#endif
#elif defined(CONFIG_POSIX_MADVISE)
#define QEMU_MADV_WILLNEED POSIX_MADV_WILLNEED
#define QEMU_MADV_DONTNEED POSIX_MADV_DONTNEED
#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID
#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID
#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID
#define QEMU_MADV_DODUMP QEMU_MADV_INVALID
#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID
#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID
#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID
#define QEMU_MADV_REMOVE QEMU_MADV_DONTNEED
#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID
#else /* no-op */
#define QEMU_MADV_WILLNEED QEMU_MADV_INVALID
#define QEMU_MADV_DONTNEED QEMU_MADV_INVALID
#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID
#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID
#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID
#define QEMU_MADV_DODUMP QEMU_MADV_INVALID
#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID
#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID
#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID
#define QEMU_MADV_REMOVE QEMU_MADV_INVALID
#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID
#endif
#ifdef _WIN32
#define HAVE_CHARDEV_SERIAL 1
#elif defined(__linux__) || defined(__sun__) || defined(__FreeBSD__) \
@ -577,11 +471,6 @@ void sigaction_invoke(struct sigaction *action,
struct qemu_signalfd_siginfo *info);
#endif
int qemu_madvise(void *addr, size_t len, int advice);
int qemu_mprotect_rw(void *addr, size_t size);
int qemu_mprotect_rwx(void *addr, size_t size);
int qemu_mprotect_none(void *addr, size_t size);
/*
* Don't introduce new usage of this function, prefer the following
* qemu_open/qemu_create that take an "Error **errp"
@ -645,22 +534,6 @@ static inline void qemu_timersub(const struct timeval *val1,
void qemu_set_cloexec(int fd);
/* Starting on QEMU 2.5, qemu_hw_version() returns "2.5+" by default
* instead of QEMU_VERSION, so setting hw_version on MachineClass
* is no longer mandatory.
*
* Do NOT change this string, or it will break compatibility on all
* machine classes that don't set hw_version.
*/
#define QEMU_HW_VERSION "2.5+"
/* QEMU "hardware version" setting. Used to replace code that exposed
* QEMU_VERSION to guests in the past and need to keep compatibility.
* Do not use qemu_hw_version() in new code.
*/
void qemu_set_hw_version(const char *);
const char *qemu_hw_version(void);
void fips_set_state(bool requested);
bool fips_get_state(void);
@ -727,11 +600,6 @@ pid_t qemu_fork(Error **errp);
extern uintptr_t qemu_real_host_page_size;
extern intptr_t qemu_real_host_page_mask;
extern int qemu_icache_linesize;
extern int qemu_icache_linesize_log;
extern int qemu_dcache_linesize;
extern int qemu_dcache_linesize_log;
/*
* After using getopt or getopt_long, if you need to parse another set
* of options, then you must reset optind. Unfortunately the way to

1
migration/postcopy-ram.c
View File

@ -18,6 +18,7 @@
#include "qemu/osdep.h"
#include "qemu/rcu.h"
#include "qemu/madvise.h"
#include "exec/target_page.h"
#include "migration.h"
#include "qemu-file.h"

1
migration/qemu-file.c
View File

@ -23,6 +23,7 @@
*/
#include "qemu/osdep.h"
#include <zlib.h>
#include "qemu/madvise.h"
#include "qemu/error-report.h"
#include "qemu/iov.h"
#include "migration.h"

1
migration/ram.c
View File

@ -30,6 +30,7 @@
#include "qemu/cutils.h"
#include "qemu/bitops.h"
#include "qemu/bitmap.h"
#include "qemu/madvise.h"
#include "qemu/main-loop.h"
#include "xbzrle.h"
#include "ram.h"

1
plugins/loader.c
View File

@ -24,6 +24,7 @@
#include "qemu/rcu_queue.h"
#include "qemu/qht.h"
#include "qemu/bitmap.h"
#include "qemu/cacheinfo.h"
#include "qemu/xxhash.h"
#include "qemu/plugin.h"
#include "hw/core/cpu.h"

4
qom/object.c
View File

@ -2793,13 +2793,13 @@ static void object_class_init(ObjectClass *klass, void *data)
static void register_types(void)
{
static TypeInfo interface_info = {
static const TypeInfo interface_info = {
.name = TYPE_INTERFACE,
.class_size = sizeof(InterfaceClass),
.abstract = true,
};
static TypeInfo object_info = {
static const TypeInfo object_info = {
.name = TYPE_OBJECT,
.instance_size = sizeof(Object),
.class_init = object_class_init,

1
scripts/checkpatch.pl
View File

@ -2882,6 +2882,7 @@ sub process {
SCSIBusInfo|
SCSIReqOps|
Spice[A-Z][a-zA-Z0-9]*Interface|
TypeInfo|
USBDesc[A-Z][a-zA-Z0-9]*|
VhostOps|
VMStateDescription|

1
softmmu/physmem.c
View File

@ -23,6 +23,7 @@
#include "qemu/cutils.h"
#include "qemu/cacheflush.h"
#include "qemu/madvise.h"
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"

1
softmmu/vl.c
View File

@ -36,6 +36,7 @@
#include "qemu-version.h"
#include "qemu/cutils.h"
#include "qemu/help_option.h"
#include "qemu/hw-version.h"
#include "qemu/uuid.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"

30
target/arm/cpu.c
View File

@ -39,7 +39,6 @@
#include "sysemu/tcg.h"
#include "sysemu/hw_accel.h"
#include "kvm_arm.h"
#include "hvf_arm.h"
#include "disas/capstone.h"
#include "fpu/softfloat.h"
@ -2079,31 +2078,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#endif /* CONFIG_TCG */
}
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
static void arm_host_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
#ifdef CONFIG_KVM
kvm_arm_set_cpu_features_from_host(cpu);
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
aarch64_add_sve_properties(obj);
aarch64_add_pauth_properties(obj);
}
#else
hvf_arm_set_cpu_features_from_host(cpu);
#endif
arm_cpu_post_init(obj);
}
static const TypeInfo host_arm_cpu_type_info = {
.name = TYPE_ARM_HOST_CPU,
.parent = TYPE_AARCH64_CPU,
.instance_init = arm_host_initfn,
};
#endif
static void arm_cpu_instance_init(Object *obj)
{
ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
@ -2151,10 +2125,6 @@ static const TypeInfo arm_cpu_type_info = {
static void arm_cpu_register_types(void)
{
type_register_static(&arm_cpu_type_info);
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
type_register_static(&host_arm_cpu_type_info);
#endif
}
type_init(arm_cpu_register_types)

331
target/arm/cpu64.c
View File

@ -29,7 +29,9 @@
#include "hw/loader.h"
#endif
#include "sysemu/kvm.h"
#include "sysemu/hvf.h"
#include "kvm_arm.h"
#include "hvf_arm.h"
#include "qapi/visitor.h"
#include "hw/qdev-properties.h"
@ -631,9 +633,10 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
uint64_t t;
/* Exit early if PAuth is enabled, and fall through to disable it */
if (kvm_enabled() && cpu->prop_pauth) {
if ((kvm_enabled() || hvf_enabled()) && cpu->prop_pauth) {
if (!cpu_isar_feature(aa64_pauth, cpu)) {
error_setg(errp, "'pauth' feature not supported by KVM on this host");
error_setg(errp, "'pauth' feature not supported by %s on this host",
kvm_enabled() ? "KVM" : "hvf");
}
return;
@ -670,10 +673,14 @@ void aarch64_add_pauth_properties(Object *obj)
/* Default to PAUTH on, with the architected algorithm on TCG. */
qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property);
if (kvm_enabled()) {
if (kvm_enabled() || hvf_enabled()) {
/*
* Mirror PAuth support from the probed sysregs back into the
* property for KVM. Is it just a bit backward? Yes it is!
* property for KVM or hvf. Is it just a bit backward? Yes it is!
* Note that prop_pauth is true whether the host CPU supports the
* architected QARMA5 algorithm or the IMPDEF one. We don't
* provide the separate pauth-impdef property for KVM or hvf,
* only for TCG.
*/
cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu);
} else {
@ -681,6 +688,24 @@ void aarch64_add_pauth_properties(Object *obj)
}
}
static void aarch64_host_initfn(Object *obj)
{
#if defined(CONFIG_KVM)
ARMCPU *cpu = ARM_CPU(obj);
kvm_arm_set_cpu_features_from_host(cpu);
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
aarch64_add_sve_properties(obj);
aarch64_add_pauth_properties(obj);
}
#elif defined(CONFIG_HVF)
ARMCPU *cpu = ARM_CPU(obj);
hvf_arm_set_cpu_features_from_host(cpu);
aarch64_add_pauth_properties(obj);
#else
g_assert_not_reached();
#endif
}
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
* otherwise, a CPU with as many features enabled as our emulation supports.
* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
@ -689,174 +714,179 @@ void aarch64_add_pauth_properties(Object *obj)
static void aarch64_max_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
uint64_t t;
uint32_t u;
if (kvm_enabled()) {
kvm_arm_set_cpu_features_from_host(cpu);
} else {
uint64_t t;
uint32_t u;
aarch64_a57_initfn(obj);
if (kvm_enabled() || hvf_enabled()) {
/* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
aarch64_host_initfn(obj);
return;
}
/*
* Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
* one and try to apply errata workarounds or use impdef features we
* don't provide.
* An IMPLEMENTER field of 0 means "reserved for software use";
* ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
* to see which features are present";
* the VARIANT, PARTNUM and REVISION fields are all implementation
* defined and we choose to define PARTNUM just in case guest
* code needs to distinguish this QEMU CPU from other software
* implementations, though this shouldn't be needed.
*/
t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
cpu->midr = t;
/* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
t = cpu->isar.id_aa64isar0;
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
cpu->isar.id_aa64isar0 = t;
aarch64_a57_initfn(obj);
t = cpu->isar.id_aa64isar1;
t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
cpu->isar.id_aa64isar1 = t;
/*
* Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
* one and try to apply errata workarounds or use impdef features we
* don't provide.
* An IMPLEMENTER field of 0 means "reserved for software use";
* ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
* to see which features are present";
* the VARIANT, PARTNUM and REVISION fields are all implementation
* defined and we choose to define PARTNUM just in case guest
* code needs to distinguish this QEMU CPU from other software
* implementations, though this shouldn't be needed.
*/
t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
cpu->midr = t;
t = cpu->isar.id_aa64pfr0;
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
cpu->isar.id_aa64pfr0 = t;
t = cpu->isar.id_aa64isar0;
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
cpu->isar.id_aa64isar0 = t;
t = cpu->isar.id_aa64pfr1;
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
/*
* Begin with full support for MTE. This will be downgraded to MTE=0
* during realize if the board provides no tag memory, much like
* we do for EL2 with the virtualization=on property.
*/
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
cpu->isar.id_aa64pfr1 = t;
t = cpu->isar.id_aa64isar1;
t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
cpu->isar.id_aa64isar1 = t;
t = cpu->isar.id_aa64mmfr0;
t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
cpu->isar.id_aa64mmfr0 = t;
t = cpu->isar.id_aa64pfr0;
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
cpu->isar.id_aa64pfr0 = t;
t = cpu->isar.id_aa64mmfr1;
t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
cpu->isar.id_aa64mmfr1 = t;
t = cpu->isar.id_aa64pfr1;
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
/*
* Begin with full support for MTE. This will be downgraded to MTE=0
* during realize if the board provides no tag memory, much like
* we do for EL2 with the virtualization=on property.
*/
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
cpu->isar.id_aa64pfr1 = t;
t = cpu->isar.id_aa64mmfr2;
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
cpu->isar.id_aa64mmfr2 = t;
t = cpu->isar.id_aa64mmfr0;
t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
cpu->isar.id_aa64mmfr0 = t;
t = cpu->isar.id_aa64zfr0;
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
cpu->isar.id_aa64zfr0 = t;
t = cpu->isar.id_aa64mmfr1;
t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
cpu->isar.id_aa64mmfr1 = t;
/* Replicate the same data to the 32-bit id registers. */
u = cpu->isar.id_isar5;
u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
cpu->isar.id_isar5 = u;
t = cpu->isar.id_aa64mmfr2;
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
cpu->isar.id_aa64mmfr2 = t;
u = cpu->isar.id_isar6;
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
u = FIELD_DP32(u, ID_ISAR6, SB, 1);
u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
cpu->isar.id_isar6 = u;
t = cpu->isar.id_aa64zfr0;
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
cpu->isar.id_aa64zfr0 = t;
u = cpu->isar.id_pfr0;
u = FIELD_DP32(u, ID_PFR0, DIT, 1);
cpu->isar.id_pfr0 = u;
/* Replicate the same data to the 32-bit id registers. */
u = cpu->isar.id_isar5;
u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
cpu->isar.id_isar5 = u;
u = cpu->isar.id_pfr2;
u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
cpu->isar.id_pfr2 = u;
u = cpu->isar.id_isar6;
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
u = FIELD_DP32(u, ID_ISAR6, SB, 1);
u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
cpu->isar.id_isar6 = u;
u = cpu->isar.id_mmfr3;
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->isar.id_mmfr3 = u;
u = cpu->isar.id_pfr0;
u = FIELD_DP32(u, ID_PFR0, DIT, 1);
cpu->isar.id_pfr0 = u;
u = cpu->isar.id_mmfr4;
u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
cpu->isar.id_mmfr4 = u;
u = cpu->isar.id_pfr2;
u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
cpu->isar.id_pfr2 = u;
t = cpu->isar.id_aa64dfr0;
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
cpu->isar.id_aa64dfr0 = t;
u = cpu->isar.id_mmfr3;
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->isar.id_mmfr3 = u;
u = cpu->isar.id_dfr0;
u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
cpu->isar.id_dfr0 = u;
u = cpu->isar.id_mmfr4;
u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
cpu->isar.id_mmfr4 = u;
u = cpu->isar.mvfr1;
u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
cpu->isar.mvfr1 = u;
t = cpu->isar.id_aa64dfr0;
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
cpu->isar.id_aa64dfr0 = t;
u = cpu->isar.id_dfr0;
u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
cpu->isar.id_dfr0 = u;
u = cpu->isar.mvfr1;
u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
cpu->isar.mvfr1 = u;
#ifdef CONFIG_USER_ONLY
/* For usermode -cpu max we can use a larger and more efficient DCZ
* blocksize since we don't have to follow what the hardware does.
*/
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
cpu->dcz_blocksize = 7; /* 512 bytes */
/*
* For usermode -cpu max we can use a larger and more efficient DCZ
* blocksize since we don't have to follow what the hardware does.
*/
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
cpu->dcz_blocksize = 7; /* 512 bytes */
#endif
bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ);
}
bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ);
aarch64_add_pauth_properties(obj);
aarch64_add_sve_properties(obj);
@ -917,6 +947,9 @@ static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
{ .name = "max", .initfn = aarch64_max_initfn },
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
{ .name = "host", .initfn = aarch64_host_initfn },
#endif
};
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)

83
target/arm/hvf/hvf.c
View File

@ -35,9 +35,34 @@
ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
#define PL1_WRITE_MASK 0x4
#define SYSREG_OP0_SHIFT 20
#define SYSREG_OP0_MASK 0x3
#define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK)
#define SYSREG_OP1_SHIFT 14
#define SYSREG_OP1_MASK 0x7
#define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK)
#define SYSREG_CRN_SHIFT 10
#define SYSREG_CRN_MASK 0xf
#define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK)
#define SYSREG_CRM_SHIFT 1
#define SYSREG_CRM_MASK 0xf
#define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK)
#define SYSREG_OP2_SHIFT 17
#define SYSREG_OP2_MASK 0x7
#define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK)
#define SYSREG(op0, op1, crn, crm, op2) \
((op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (crm << 1))
#define SYSREG_MASK SYSREG(0x3, 0x7, 0xf, 0xf, 0x7)
((op0 << SYSREG_OP0_SHIFT) | \
(op1 << SYSREG_OP1_SHIFT) | \
(crn << SYSREG_CRN_SHIFT) | \
(crm << SYSREG_CRM_SHIFT) | \
(op2 << SYSREG_OP2_SHIFT))
#define SYSREG_MASK \
SYSREG(SYSREG_OP0_MASK, \
SYSREG_OP1_MASK, \
SYSREG_CRN_MASK, \
SYSREG_CRM_MASK, \
SYSREG_OP2_MASK)
#define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4)
#define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4)
#define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)
@ -729,6 +754,15 @@ static bool hvf_handle_psci_call(CPUState *cpu)
return true;
}
static bool is_id_sysreg(uint32_t reg)
{
return SYSREG_OP0(reg) == 3 &&
SYSREG_OP1(reg) == 0 &&
SYSREG_CRN(reg) == 0 &&
SYSREG_CRM(reg) >= 1 &&
SYSREG_CRM(reg) < 8;
}
static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
{
ARMCPU *arm_cpu = ARM_CPU(cpu);
@ -781,23 +815,28 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
/* Dummy register */
break;
default:
if (is_id_sysreg(reg)) {
/* ID system registers read as RES0 */
val = 0;
break;
}
cpu_synchronize_state(cpu);
trace_hvf_unhandled_sysreg_read(env->pc, reg,
(reg >> 20) & 0x3,
(reg >> 14) & 0x7,
(reg >> 10) & 0xf,
(reg >> 1) & 0xf,
(reg >> 17) & 0x7);
SYSREG_OP0(reg),
SYSREG_OP1(reg),
SYSREG_CRN(reg),
SYSREG_CRM(reg),
SYSREG_OP2(reg));
hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
return 1;
}
trace_hvf_sysreg_read(reg,
(reg >> 20) & 0x3,
(reg >> 14) & 0x7,
(reg >> 10) & 0xf,
(reg >> 1) & 0xf,
(reg >> 17) & 0x7,
SYSREG_OP0(reg),
SYSREG_OP1(reg),
SYSREG_CRN(reg),
SYSREG_CRM(reg),
SYSREG_OP2(reg),
val);
hvf_set_reg(cpu, rt, val);
@ -886,11 +925,11 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
CPUARMState *env = &arm_cpu->env;
trace_hvf_sysreg_write(reg,
(reg >> 20) & 0x3,
(reg >> 14) & 0x7,
(reg >> 10) & 0xf,
(reg >> 1) & 0xf,
(reg >> 17) & 0x7,
SYSREG_OP0(reg),
SYSREG_OP1(reg),
SYSREG_CRN(reg),
SYSREG_CRM(reg),
SYSREG_OP2(reg),
val);
switch (reg) {
@ -960,11 +999,11 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
default:
cpu_synchronize_state(cpu);
trace_hvf_unhandled_sysreg_write(env->pc, reg,
(reg >> 20) & 0x3,
(reg >> 14) & 0x7,
(reg >> 10) & 0xf,
(reg >> 1) & 0xf,
(reg >> 17) & 0x7);
SYSREG_OP0(reg),
SYSREG_OP1(reg),
SYSREG_CRN(reg),
SYSREG_CRM(reg),
SYSREG_OP2(reg));
hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
return 1;
}

1
target/i386/cpu.c
View File

@ -21,6 +21,7 @@
#include "qemu/units.h"
#include "qemu/cutils.h"
#include "qemu/qemu-print.h"
#include "qemu/hw-version.h"
#include "cpu.h"
#include "tcg/helper-tcg.h"
#include "sysemu/reset.h"

1
target/s390x/cpu_models.c
View File

@ -19,6 +19,7 @@
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "qemu/module.h"
#include "qemu/hw-version.h"
#include "qemu/qemu-print.h"
#ifndef CONFIG_USER_ONLY
#include "sysemu/sysemu.h"

3
tcg/region.c
View File

@ -24,6 +24,9 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/madvise.h"
#include "qemu/mprotect.h"
#include "qemu/cacheinfo.h"
#include "qapi/error.h"
#include "exec/exec-all.h"
#include "tcg/tcg.h"

1
tcg/tcg.c
View File

@ -36,6 +36,7 @@
#include "qemu/qemu-print.h"
#include "qemu/timer.h"
#include "qemu/cacheflush.h"
#include "qemu/cacheinfo.h"
/* Note: the long term plan is to reduce the dependencies on the QEMU
CPU definitions. Currently they are used for qemu_ld/st

15
ui/cocoa.m
View File

@ -100,7 +100,6 @@ static int gArgc;
static char **gArgv;
static bool stretch_video;
static NSTextField *pauseLabel;
static NSArray * supportedImageFileTypes;
static QemuSemaphore display_init_sem;
static QemuSemaphore app_started_sem;
@ -1168,10 +1167,6 @@ QemuCocoaView *cocoaView;
[pauseLabel setTextColor: [NSColor blackColor]];
[pauseLabel sizeToFit];
// set the supported image file types that can be opened
supportedImageFileTypes = [NSArray arrayWithObjects: @"img", @"iso", @"dmg",
@"qcow", @"qcow2", @"cloop", @"vmdk", @"cdr",
@"toast", nil];
[self make_about_window];
}
return self;
@ -1414,7 +1409,6 @@ QemuCocoaView *cocoaView;
openPanel = [NSOpenPanel openPanel];
[openPanel setCanChooseFiles: YES];
[openPanel setAllowsMultipleSelection: NO];
[openPanel setAllowedFileTypes: supportedImageFileTypes];
if([openPanel runModal] == NSModalResponseOK) {
NSString * file = [[[openPanel URLs] objectAtIndex: 0] path];
if(file == nil) {
@ -1680,7 +1674,9 @@ static void create_initial_menus(void)
/* Returns a name for a given console */
static NSString * getConsoleName(QemuConsole * console)
{
return [NSString stringWithFormat: @"%s", qemu_console_get_label(console)];
g_autofree char *label = qemu_console_get_label(console);
return [NSString stringWithUTF8String:label];
}
/* Add an entry to the View menu for each console */
@ -1715,11 +1711,6 @@ static void addRemovableDevicesMenuItems(void)
currentDevice = qmp_query_block(NULL);
pointerToFree = currentDevice;
if(currentDevice == NULL) {
NSBeep();
QEMU_Alert(@"Failed to query for block devices!");
return;
}
menu = [[[NSApp mainMenu] itemWithTitle:@"Machine"] submenu];

1
util/atomic64.c
View File

@ -7,6 +7,7 @@
#include "qemu/osdep.h"
#include "qemu/atomic.h"
#include "qemu/thread.h"
#include "qemu/cacheinfo.h"
#ifdef CONFIG_ATOMIC64
#error This file must only be compiled if !CONFIG_ATOMIC64

1
util/cacheflush.c
View File

@ -7,6 +7,7 @@
#include "qemu/osdep.h"
#include "qemu/cacheflush.h"
#include "qemu/cacheinfo.h"
#include "qemu/bitops.h"

1
util/cacheinfo.c
View File

@ -9,6 +9,7 @@
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
#include "qemu/atomic.h"
#include "qemu/cacheinfo.h"
int qemu_icache_linesize = 0;
int qemu_icache_linesize_log;

3
util/osdep.c
View File

@ -38,6 +38,9 @@ extern int madvise(char *, size_t, int);
#include "qemu/cutils.h"
#include "qemu/sockets.h"
#include "qemu/error-report.h"
#include "qemu/madvise.h"
#include "qemu/mprotect.h"
#include "qemu/hw-version.h"
#include "monitor/monitor.h"
static bool fips_enabled = false;

1
util/oslib-posix.c
View File

@ -36,6 +36,7 @@
#include "trace.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/madvise.h"
#include "qemu/sockets.h"
#include "qemu/thread.h"
#include <libgen.h>