target/arm: Convert conditional branch insns to decodetree
Convert the immediate conditional branch insn B.cond to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-17-peter.maydell@linaro.org
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@ -124,3 +124,5 @@ CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19
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&tbz rt imm nz bitpos
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TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19
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B_cond 0101010 0 ................... 0 cond:4 imm=%imm19
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@ -1371,36 +1371,21 @@ static bool trans_TBZ(DisasContext *s, arg_tbz *a)
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return true;
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}
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/* Conditional branch (immediate)
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* 31 25 24 23 5 4 3 0
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* +---------------+----+---------------------+----+------+
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* | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
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* +---------------+----+---------------------+----+------+
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*/
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static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
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static bool trans_B_cond(DisasContext *s, arg_B_cond *a)
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{
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unsigned int cond;
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int64_t diff;
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if ((insn & (1 << 4)) || (insn & (1 << 24))) {
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unallocated_encoding(s);
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return;
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}
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diff = sextract32(insn, 5, 19) * 4;
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cond = extract32(insn, 0, 4);
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reset_btype(s);
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if (cond < 0x0e) {
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if (a->cond < 0x0e) {
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/* genuinely conditional branches */
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DisasLabel match = gen_disas_label(s);
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arm_gen_test_cc(cond, match.label);
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arm_gen_test_cc(a->cond, match.label);
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gen_goto_tb(s, 0, 4);
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set_disas_label(s, match);
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gen_goto_tb(s, 1, diff);
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gen_goto_tb(s, 1, a->imm);
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} else {
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/* 0xe and 0xf are both "always" conditions */
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gen_goto_tb(s, 0, diff);
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gen_goto_tb(s, 0, a->imm);
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}
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return true;
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}
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/* HINT instruction group, including various allocated HINTs */
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@ -2385,9 +2370,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
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static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
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{
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switch (extract32(insn, 25, 7)) {
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case 0x2a: /* Conditional branch (immediate) */
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disas_cond_b_imm(s, insn);
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break;
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case 0x6a: /* Exception generation / System */
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if (insn & (1 << 24)) {
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if (extract32(insn, 22, 2) == 0) {
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