hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink
In order to use inclusive terminology, rename 'slave stream' as 'sink stream'. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20200910070131.435543-4-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -45,11 +45,11 @@
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OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIDMA, XILINX_AXI_DMA)
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OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIDMA, XILINX_AXI_DMA)
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typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
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typedef struct XilinxAXIDMAStreamSink XilinxAXIDMAStreamSink;
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DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSlave, XILINX_AXI_DMA_DATA_STREAM,
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DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSink, XILINX_AXI_DMA_DATA_STREAM,
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TYPE_XILINX_AXI_DMA_DATA_STREAM)
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TYPE_XILINX_AXI_DMA_DATA_STREAM)
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DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSlave, XILINX_AXI_DMA_CONTROL_STREAM,
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DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSink, XILINX_AXI_DMA_CONTROL_STREAM,
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TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
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TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
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#define R_DMACR (0x00 / 4)
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#define R_DMACR (0x00 / 4)
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@ -115,7 +115,7 @@ struct Stream {
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unsigned char txbuf[16 * 1024];
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unsigned char txbuf[16 * 1024];
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};
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};
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struct XilinxAXIDMAStreamSlave {
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struct XilinxAXIDMAStreamSink {
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Object parent;
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Object parent;
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struct XilinxAXIDMA *dma;
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struct XilinxAXIDMA *dma;
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@ -130,8 +130,8 @@ struct XilinxAXIDMA {
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uint32_t freqhz;
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uint32_t freqhz;
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StreamSink *tx_data_dev;
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StreamSink *tx_data_dev;
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StreamSink *tx_control_dev;
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StreamSink *tx_control_dev;
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XilinxAXIDMAStreamSlave rx_data_dev;
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XilinxAXIDMAStreamSink rx_data_dev;
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XilinxAXIDMAStreamSlave rx_control_dev;
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XilinxAXIDMAStreamSink rx_control_dev;
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struct Stream streams[2];
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struct Stream streams[2];
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@ -387,7 +387,7 @@ static size_t
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xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf,
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xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf,
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size_t len, bool eop)
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size_t len, bool eop)
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{
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{
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XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
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XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
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struct Stream *s = &cs->dma->streams[1];
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struct Stream *s = &cs->dma->streams[1];
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if (len != CONTROL_PAYLOAD_SIZE) {
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if (len != CONTROL_PAYLOAD_SIZE) {
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@ -404,7 +404,7 @@ xilinx_axidma_data_stream_can_push(StreamSink *obj,
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StreamCanPushNotifyFn notify,
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StreamCanPushNotifyFn notify,
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void *notify_opaque)
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void *notify_opaque)
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{
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{
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XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
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XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
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struct Stream *s = &ds->dma->streams[1];
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struct Stream *s = &ds->dma->streams[1];
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if (!stream_running(s) || stream_idle(s)) {
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if (!stream_running(s) || stream_idle(s)) {
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@ -420,7 +420,7 @@ static size_t
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xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len,
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xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len,
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bool eop)
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bool eop)
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{
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{
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XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
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XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
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struct Stream *s = &ds->dma->streams[1];
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struct Stream *s = &ds->dma->streams[1];
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size_t ret;
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size_t ret;
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@ -531,8 +531,8 @@ static const MemoryRegionOps axidma_ops = {
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static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
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static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
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{
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{
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XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
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XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
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XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
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XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
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XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
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XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(
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&s->rx_control_dev);
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&s->rx_control_dev);
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int i;
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int i;
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@ -631,7 +631,7 @@ static const TypeInfo axidma_info = {
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static const TypeInfo xilinx_axidma_data_stream_info = {
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static const TypeInfo xilinx_axidma_data_stream_info = {
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.name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
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.name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
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.parent = TYPE_OBJECT,
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.parent = TYPE_OBJECT,
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.instance_size = sizeof(XilinxAXIDMAStreamSlave),
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.instance_size = sizeof(XilinxAXIDMAStreamSink),
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.class_init = xilinx_axidma_stream_class_init,
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.class_init = xilinx_axidma_stream_class_init,
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.class_data = &xilinx_axidma_data_stream_class,
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.class_data = &xilinx_axidma_data_stream_class,
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.interfaces = (InterfaceInfo[]) {
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.interfaces = (InterfaceInfo[]) {
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@ -643,7 +643,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = {
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static const TypeInfo xilinx_axidma_control_stream_info = {
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static const TypeInfo xilinx_axidma_control_stream_info = {
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.name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
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.name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
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.parent = TYPE_OBJECT,
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.parent = TYPE_OBJECT,
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.instance_size = sizeof(XilinxAXIDMAStreamSlave),
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.instance_size = sizeof(XilinxAXIDMAStreamSink),
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.class_init = xilinx_axidma_stream_class_init,
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.class_init = xilinx_axidma_stream_class_init,
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.class_data = &xilinx_axidma_control_stream_class,
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.class_data = &xilinx_axidma_control_stream_class,
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.interfaces = (InterfaceInfo[]) {
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.interfaces = (InterfaceInfo[]) {
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