target/arm: Introduce gen_exception_insn
Create a new wrapper function that passes the default exception target to gen_exception_insn_el. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1816,8 +1816,7 @@ static void gen_sysreg_undef(DisasContext *s, bool isread,
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} else {
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} else {
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syndrome = syn_uncategorized();
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syndrome = syn_uncategorized();
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}
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}
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome,
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome);
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default_exception_el(s));
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}
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}
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/* MRS - move from system register
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/* MRS - move from system register
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@ -2069,8 +2068,8 @@ static void disas_exc(DisasContext *s, uint32_t insn)
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switch (op2_ll) {
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switch (op2_ll) {
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case 1: /* SVC */
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case 1: /* SVC */
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gen_ss_advance(s);
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gen_ss_advance(s);
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gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI,
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gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
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syn_aa64_svc(imm16), default_exception_el(s));
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syn_aa64_svc(imm16));
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break;
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break;
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case 2: /* HVC */
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case 2: /* HVC */
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if (s->current_el == 0) {
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if (s->current_el == 0) {
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@ -14725,8 +14724,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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* Illegal execution state. This has priority over BTI
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* Illegal execution state. This has priority over BTI
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* exceptions, but comes after instruction abort exceptions.
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* exceptions, but comes after instruction abort exceptions.
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*/
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*/
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate());
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syn_illegalstate(), default_exception_el(s));
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return;
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return;
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}
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}
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@ -14757,9 +14755,8 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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if (s->btype != 0
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if (s->btype != 0
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&& s->guarded_page
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&& s->guarded_page
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&& !btype_destination_ok(insn, s->bt, s->btype)) {
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&& !btype_destination_ok(insn, s->bt, s->btype)) {
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
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syn_btitrap(s->btype),
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syn_btitrap(s->btype));
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default_exception_el(s));
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return;
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return;
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}
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}
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} else {
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} else {
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@ -765,8 +765,7 @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a)
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}
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}
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if (a->cp != 10) {
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if (a->cp != 10) {
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gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized());
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syn_uncategorized(), default_exception_el(s));
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return true;
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return true;
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}
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}
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@ -100,8 +100,7 @@ bool mve_eci_check(DisasContext *s)
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return true;
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return true;
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default:
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default:
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/* Reserved value: INVSTATE UsageFault */
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/* Reserved value: INVSTATE UsageFault */
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gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
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default_exception_el(s));
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return false;
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return false;
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}
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}
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}
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}
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@ -1106,6 +1106,11 @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
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gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
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gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
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}
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}
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void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
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{
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gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s));
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}
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static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
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static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
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{
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{
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gen_set_condexec(s);
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gen_set_condexec(s);
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@ -1117,8 +1122,7 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
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void unallocated_encoding(DisasContext *s)
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void unallocated_encoding(DisasContext *s)
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{
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{
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/* Unallocated and reserved encodings are uncategorized */
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/* Unallocated and reserved encodings are uncategorized */
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized());
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default_exception_el(s));
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}
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}
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/* Force a TB lookup after an instruction that changes the CPU state. */
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/* Force a TB lookup after an instruction that changes the CPU state. */
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@ -2731,8 +2735,6 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
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* an exception and return false. Otherwise it will return true,
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* an exception and return false. Otherwise it will return true,
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* and set *tgtmode and *regno appropriately.
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* and set *tgtmode and *regno appropriately.
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*/
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*/
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int exc_target = default_exception_el(s);
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/* These instructions are present only in ARMv8, or in ARMv7 with the
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/* These instructions are present only in ARMv8, or in ARMv7 with the
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* Virtualization Extensions.
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* Virtualization Extensions.
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*/
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*/
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@ -2869,8 +2871,7 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
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undef:
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undef:
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/* If we get here then some access check did not pass */
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/* If we get here then some access check did not pass */
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized());
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syn_uncategorized(), exc_target);
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return false;
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return false;
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}
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}
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@ -8583,8 +8584,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
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tmp = load_cpu_field(v7m.ltpsize);
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tmp = load_cpu_field(v7m.ltpsize);
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tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
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tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(tmp);
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gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
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default_exception_el(s));
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gen_set_label(skipexc);
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gen_set_label(skipexc);
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}
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}
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@ -9054,8 +9054,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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* UsageFault exception.
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* UsageFault exception.
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*/
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*/
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if (arm_dc_feature(s, ARM_FEATURE_M)) {
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if (arm_dc_feature(s, ARM_FEATURE_M)) {
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gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
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default_exception_el(s));
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return;
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return;
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}
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}
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@ -9064,8 +9063,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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* Illegal execution state. This has priority over BTI
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* Illegal execution state. This has priority over BTI
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* exceptions, but comes after instruction abort exceptions.
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* exceptions, but comes after instruction abort exceptions.
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*/
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*/
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate());
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syn_illegalstate(), default_exception_el(s));
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return;
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return;
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}
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}
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@ -9634,8 +9632,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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* Illegal execution state. This has priority over BTI
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* Illegal execution state. This has priority over BTI
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* exceptions, but comes after instruction abort exceptions.
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* exceptions, but comes after instruction abort exceptions.
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*/
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*/
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gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF,
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gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, syn_illegalstate());
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syn_illegalstate(), default_exception_el(dc));
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return;
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return;
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}
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}
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@ -9708,8 +9705,8 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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*/
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*/
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tcg_remove_ops_after(dc->insn_eci_rewind);
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tcg_remove_ops_after(dc->insn_eci_rewind);
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dc->condjmp = 0;
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dc->condjmp = 0;
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gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE,
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default_exception_el(dc));
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syn_uncategorized());
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}
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}
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arm_post_translate_insn(dc);
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arm_post_translate_insn(dc);
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@ -281,6 +281,7 @@ MemOp pow2_align(unsigned i);
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void unallocated_encoding(DisasContext *s);
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void unallocated_encoding(DisasContext *s);
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void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
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void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
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uint32_t syn, uint32_t target_el);
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uint32_t syn, uint32_t target_el);
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void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn);
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/* Return state of Alternate Half-precision flag, caller frees result */
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/* Return state of Alternate Half-precision flag, caller frees result */
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static inline TCGv_i32 get_ahp_flag(void)
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static inline TCGv_i32 get_ahp_flag(void)
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