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target-ppc: consolidate load with reservation

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Use tcg_gen_qemu_ld in the load with reservation instructions.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Nikunj A Dadhania 2016-09-12 12:11:36 +05:30 committed by David Gibson
parent 804108aaf9
commit 48793c95c9
1 changed files with 11 additions and 11 deletions
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22
target-ppc/translate.c
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@ -3049,28 +3049,30 @@ static void gen_isync(DisasContext *ctx)
gen_stop_exception(ctx); gen_stop_exception(ctx);
} }
#define LARX(name, len, loadop) \ #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
#define LARX(name, memop) \
static void gen_##name(DisasContext *ctx) \ static void gen_##name(DisasContext *ctx) \
{ \ { \
TCGv t0; \ TCGv t0; \
TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
int len = MEMOP_GET_SIZE(memop); \
gen_set_access_type(ctx, ACCESS_RES); \ gen_set_access_type(ctx, ACCESS_RES); \
t0 = tcg_temp_local_new(); \ t0 = tcg_temp_local_new(); \
gen_addr_reg_index(ctx, t0); \ gen_addr_reg_index(ctx, t0); \
if ((len) > 1) { \ if ((len) > 1) { \
gen_check_align(ctx, t0, (len)-1); \ gen_check_align(ctx, t0, (len)-1); \
} \ } \
gen_qemu_##loadop(ctx, gpr, t0); \ tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
tcg_gen_mov_tl(cpu_reserve, t0); \ tcg_gen_mov_tl(cpu_reserve, t0); \
tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \ tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
tcg_temp_free(t0); \ tcg_temp_free(t0); \
} }
/* lwarx */ /* lwarx */
LARX(lbarx, 1, ld8u); LARX(lbarx, DEF_MEMOP(MO_UB))
LARX(lharx, 2, ld16u); LARX(lharx, DEF_MEMOP(MO_UW))
LARX(lwarx, 4, ld32u); LARX(lwarx, DEF_MEMOP(MO_UL))
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
static void gen_conditional_store(DisasContext *ctx, TCGv EA, static void gen_conditional_store(DisasContext *ctx, TCGv EA,
@ -3152,7 +3154,7 @@ STCX(stwcx_, 4);
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
/* ldarx */ /* ldarx */
LARX(ldarx, 8, ld64_i64); LARX(ldarx, DEF_MEMOP(MO_Q))
/* lqarx */ /* lqarx */
static void gen_lqarx(DisasContext *ctx) static void gen_lqarx(DisasContext *ctx)
@ -3178,15 +3180,13 @@ static void gen_lqarx(DisasContext *ctx)
gpr1 = cpu_gpr[rd]; gpr1 = cpu_gpr[rd];
gpr2 = cpu_gpr[rd+1]; gpr2 = cpu_gpr[rd+1];
} }
gen_qemu_ld64_i64(ctx, gpr1, EA); tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
tcg_gen_mov_tl(cpu_reserve, EA); tcg_gen_mov_tl(cpu_reserve, EA);
gen_addr_add(ctx, EA, EA, 8); gen_addr_add(ctx, EA, EA, 8);
gen_qemu_ld64_i64(ctx, gpr2, EA); tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
tcg_temp_free(EA); tcg_temp_free(EA);
} }