hw/sd/pxa2xx_mmci: add read/write() trace events
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 20180104000156.30932-1-f4bug@amsat.org [PMM: add missing include] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -19,6 +19,8 @@
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#include "hw/qdev.h"
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#include "hw/qdev-properties.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "trace.h"
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#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
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#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
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@ -278,45 +280,56 @@ static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
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static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
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{
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PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
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uint32_t ret;
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uint32_t ret = 0;
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switch (offset) {
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case MMC_STRPCL:
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return 0;
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break;
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case MMC_STAT:
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return s->status;
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ret = s->status;
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break;
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case MMC_CLKRT:
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return s->clkrt;
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ret = s->clkrt;
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break;
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case MMC_SPI:
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return s->spi;
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ret = s->spi;
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break;
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case MMC_CMDAT:
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return s->cmdat;
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ret = s->cmdat;
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break;
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case MMC_RESTO:
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return s->resp_tout;
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ret = s->resp_tout;
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break;
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case MMC_RDTO:
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return s->read_tout;
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ret = s->read_tout;
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break;
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case MMC_BLKLEN:
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return s->blklen;
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ret = s->blklen;
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break;
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case MMC_NUMBLK:
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return s->numblk;
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ret = s->numblk;
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break;
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case MMC_PRTBUF:
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return 0;
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break;
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case MMC_I_MASK:
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return s->intmask;
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ret = s->intmask;
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break;
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case MMC_I_REG:
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return s->intreq;
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ret = s->intreq;
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break;
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case MMC_CMD:
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return s->cmd | 0x40;
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ret = s->cmd | 0x40;
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break;
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case MMC_ARGH:
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return s->arg >> 16;
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ret = s->arg >> 16;
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break;
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case MMC_ARGL:
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return s->arg & 0xffff;
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ret = s->arg & 0xffff;
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break;
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case MMC_RES:
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if (s->resp_len < 9)
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return s->resp_fifo[s->resp_len ++];
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return 0;
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ret = (s->resp_len < 9) ? s->resp_fifo[s->resp_len++] : 0;
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break;
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case MMC_RXFIFO:
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ret = 0;
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while (size-- && s->rx_len) {
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ret |= s->rx_fifo[s->rx_start++] << (size << 3);
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s->rx_start &= 0x1f;
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@ -324,16 +337,20 @@ static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
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}
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s->intreq &= ~INT_RXFIFO_REQ;
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pxa2xx_mmci_fifo_update(s);
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return ret;
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break;
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case MMC_RDWAIT:
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return 0;
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break;
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case MMC_BLKS_REM:
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return s->numblk;
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ret = s->numblk;
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break;
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default:
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hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: incorrect register 0x%02" HWADDR_PRIx "\n",
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__func__, offset);
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}
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trace_pxa2xx_mmci_read(size, offset, ret);
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return 0;
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return ret;
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}
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static void pxa2xx_mmci_write(void *opaque,
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@ -341,6 +358,7 @@ static void pxa2xx_mmci_write(void *opaque,
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{
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PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
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trace_pxa2xx_mmci_write(size, offset, value);
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switch (offset) {
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case MMC_STRPCL:
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if (value & STRPCL_STRT_CLK) {
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@ -368,8 +386,10 @@ static void pxa2xx_mmci_write(void *opaque,
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case MMC_SPI:
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s->spi = value & 0xf;
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if (value & SPI_SPI_MODE)
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printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
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if (value & SPI_SPI_MODE) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: attempted to use card in SPI mode\n", __func__);
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}
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break;
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case MMC_CMDAT:
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@ -442,7 +462,9 @@ static void pxa2xx_mmci_write(void *opaque,
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break;
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default:
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hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: incorrect reg 0x%02" HWADDR_PRIx " "
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"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
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}
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}
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@ -3,3 +3,7 @@
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# hw/sd/milkymist-memcard.c
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milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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# hw/sd/pxa2xx_mmci.c
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pxa2xx_mmci_read(uint8_t size, uint32_t addr, uint32_t value) "size %d addr 0x%02x value 0x%08x"
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pxa2xx_mmci_write(uint8_t size, uint32_t addr, uint32_t value) "size %d addr 0x%02x value 0x%08x"
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