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hw/sd/pxa2xx_mmci: add read/write() trace events

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Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 20180104000156.30932-1-f4bug@amsat.org
[PMM: add missing include]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2018-01-11 13:25:39 +00:00 committed by Peter Maydell
parent 2ba63e4af6
commit 487b406af1
2 changed files with 54 additions and 28 deletions
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78
hw/sd/pxa2xx_mmci.c
View File

@ -19,6 +19,8 @@
#include "hw/qdev.h" #include "hw/qdev.h"
#include "hw/qdev-properties.h" #include "hw/qdev-properties.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qemu/log.h"
#include "trace.h"
#define TYPE_PXA2XX_MMCI "pxa2xx-mmci" #define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI) #define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
@ -278,45 +280,56 @@ static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size) static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
{ {
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
uint32_t ret; uint32_t ret = 0;
switch (offset) { switch (offset) {
case MMC_STRPCL: case MMC_STRPCL:
return 0; break;
case MMC_STAT: case MMC_STAT:
return s->status; ret = s->status;
break;
case MMC_CLKRT: case MMC_CLKRT:
return s->clkrt; ret = s->clkrt;
break;
case MMC_SPI: case MMC_SPI:
return s->spi; ret = s->spi;
break;
case MMC_CMDAT: case MMC_CMDAT:
return s->cmdat; ret = s->cmdat;
break;
case MMC_RESTO: case MMC_RESTO:
return s->resp_tout; ret = s->resp_tout;
break;
case MMC_RDTO: case MMC_RDTO:
return s->read_tout; ret = s->read_tout;
break;
case MMC_BLKLEN: case MMC_BLKLEN:
return s->blklen; ret = s->blklen;
break;
case MMC_NUMBLK: case MMC_NUMBLK:
return s->numblk; ret = s->numblk;
break;
case MMC_PRTBUF: case MMC_PRTBUF:
return 0; break;
case MMC_I_MASK: case MMC_I_MASK:
return s->intmask; ret = s->intmask;
break;
case MMC_I_REG: case MMC_I_REG:
return s->intreq; ret = s->intreq;
break;
case MMC_CMD: case MMC_CMD:
return s->cmd | 0x40; ret = s->cmd | 0x40;
break;
case MMC_ARGH: case MMC_ARGH:
return s->arg >> 16; ret = s->arg >> 16;
break;
case MMC_ARGL: case MMC_ARGL:
return s->arg & 0xffff; ret = s->arg & 0xffff;
break;
case MMC_RES: case MMC_RES:
if (s->resp_len < 9) ret = (s->resp_len < 9) ? s->resp_fifo[s->resp_len++] : 0;
return s->resp_fifo[s->resp_len ++]; break;
return 0;
case MMC_RXFIFO: case MMC_RXFIFO:
ret = 0;
while (size-- && s->rx_len) { while (size-- && s->rx_len) {
ret |= s->rx_fifo[s->rx_start++] << (size << 3); ret |= s->rx_fifo[s->rx_start++] << (size << 3);
s->rx_start &= 0x1f; s->rx_start &= 0x1f;
@ -324,16 +337,20 @@ static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
} }
s->intreq &= ~INT_RXFIFO_REQ; s->intreq &= ~INT_RXFIFO_REQ;
pxa2xx_mmci_fifo_update(s); pxa2xx_mmci_fifo_update(s);
return ret; break;
case MMC_RDWAIT: case MMC_RDWAIT:
return 0; break;
case MMC_BLKS_REM: case MMC_BLKS_REM:
return s->numblk; ret = s->numblk;
break;
default: default:
hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: incorrect register 0x%02" HWADDR_PRIx "\n",
__func__, offset);
} }
trace_pxa2xx_mmci_read(size, offset, ret);
return 0; return ret;
} }
static void pxa2xx_mmci_write(void *opaque, static void pxa2xx_mmci_write(void *opaque,
@ -341,6 +358,7 @@ static void pxa2xx_mmci_write(void *opaque,
{ {
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
trace_pxa2xx_mmci_write(size, offset, value);
switch (offset) { switch (offset) {
case MMC_STRPCL: case MMC_STRPCL:
if (value & STRPCL_STRT_CLK) { if (value & STRPCL_STRT_CLK) {
@ -368,8 +386,10 @@ static void pxa2xx_mmci_write(void *opaque,
case MMC_SPI: case MMC_SPI:
s->spi = value & 0xf; s->spi = value & 0xf;
if (value & SPI_SPI_MODE) if (value & SPI_SPI_MODE) {
printf("%s: attempted to use card in SPI mode\n", __FUNCTION__); qemu_log_mask(LOG_GUEST_ERROR,
"%s: attempted to use card in SPI mode\n", __func__);
}
break; break;
case MMC_CMDAT: case MMC_CMDAT:
@ -442,7 +462,9 @@ static void pxa2xx_mmci_write(void *opaque,
break; break;
default: default:
hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: incorrect reg 0x%02" HWADDR_PRIx " "
"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
} }
} }

4
hw/sd/trace-events
View File

@ -3,3 +3,7 @@
# hw/sd/milkymist-memcard.c # hw/sd/milkymist-memcard.c
milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
# hw/sd/pxa2xx_mmci.c
pxa2xx_mmci_read(uint8_t size, uint32_t addr, uint32_t value) "size %d addr 0x%02x value 0x%08x"
pxa2xx_mmci_write(uint8_t size, uint32_t addr, uint32_t value) "size %d addr 0x%02x value 0x%08x"