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target/arm: Make sure that commpage's tb->size != 0 

tb_gen_code() assumes that tb->size must never be zero, otherwise it
may produce spurious exceptions. For ARM this may happen when creating
a translation block for the commpage.

Fix by pretending that commpage translation blocks have at least one
instruction.

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210416154939.32404-3-iii@linux.ibm.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
This commit is contained in:
Ilya Leoshkevich 2021-04-16 17:49:37 +02:00 committed by Cornelia Huck
parent 86131c71b1
commit 48a130923c
1 changed files with 2 additions and 0 deletions
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2
target/arm/translate.c
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@ -8981,6 +8981,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
unsigned int insn;
if (arm_pre_translate_insn(dc)) {
dc->base.pc_next += 4;
return;
}
@ -9050,6 +9051,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
bool is_16bit;
if (arm_pre_translate_insn(dc)) {
dc->base.pc_next += 2;
return;
}