target/arm: Add ptw_idx to S1Translate
Hoist the computation of the mmu_idx for the ptw up to get_phys_addr_with_struct and get_phys_addr_twostage. This removes the duplicate check for stage2 disabled from the middle of the walk, performing it only once. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20221024051851.3074715-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -17,6 +17,7 @@
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typedef struct S1Translate {
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ARMMMUIdx in_mmu_idx;
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ARMMMUIdx in_ptw_idx;
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bool in_secure;
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bool in_debug;
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bool out_secure;
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@ -214,33 +215,24 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
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{
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bool is_secure = ptw->in_secure;
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ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
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ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
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bool s2_phys = false;
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ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx;
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uint8_t pte_attrs;
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bool pte_secure;
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if (!arm_mmu_idx_is_stage1_of_2(mmu_idx)
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|| regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
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s2_mmu_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS;
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s2_phys = true;
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}
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if (unlikely(ptw->in_debug)) {
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/*
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* From gdbstub, do not use softmmu so that we don't modify the
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* state of the cpu at all, including softmmu tlb contents.
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*/
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if (s2_phys) {
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ptw->out_phys = addr;
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pte_attrs = 0;
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pte_secure = is_secure;
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} else {
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if (regime_is_stage2(s2_mmu_idx)) {
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S1Translate s2ptw = {
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.in_mmu_idx = s2_mmu_idx,
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.in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS,
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.in_secure = is_secure,
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.in_debug = true,
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};
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GetPhysAddrResult s2 = { };
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if (!get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
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false, &s2, fi)) {
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goto fail;
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@ -248,6 +240,11 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
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ptw->out_phys = s2.f.phys_addr;
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pte_attrs = s2.cacheattrs.attrs;
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pte_secure = s2.f.attrs.secure;
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} else {
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/* Regime is physical. */
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ptw->out_phys = addr;
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pte_attrs = 0;
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pte_secure = is_secure;
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}
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ptw->out_host = NULL;
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} else {
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@ -268,7 +265,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
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pte_secure = full->attrs.secure;
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}
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if (!s2_phys) {
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if (regime_is_stage2(s2_mmu_idx)) {
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uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure);
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if ((hcr & HCR_PTW) && S2_attrs_are_device(hcr, pte_attrs)) {
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@ -1263,7 +1260,18 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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descaddr |= (address >> (stride * (4 - level))) & indexmask;
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descaddr &= ~7ULL;
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nstable = extract32(tableattrs, 4, 1);
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ptw->in_secure = !nstable;
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if (!nstable) {
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/*
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* Stage2_S -> Stage2 or Phys_S -> Phys_NS
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* Assert that the non-secure idx are even, and relative order.
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*/
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QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS & 1) != 0);
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QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2 & 1) != 0);
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QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS + 1 != ARMMMUIdx_Phys_S);
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QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2 + 1 != ARMMMUIdx_Stage2_S);
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ptw->in_ptw_idx &= ~1;
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ptw->in_secure = false;
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}
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descriptor = arm_ldq_ptw(env, ptw, descaddr, fi);
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if (fi->type != ARMFault_None) {
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goto do_fault;
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@ -2449,6 +2457,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
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is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
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ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
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ptw->in_ptw_idx = s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS;
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ptw->in_secure = s2walk_secure;
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/*
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@ -2508,10 +2517,32 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
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ARMMMUFaultInfo *fi)
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{
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ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
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ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
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bool is_secure = ptw->in_secure;
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ARMMMUIdx s1_mmu_idx;
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if (mmu_idx != s1_mmu_idx) {
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switch (mmu_idx) {
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case ARMMMUIdx_Phys_S:
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case ARMMMUIdx_Phys_NS:
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/* Checking Phys early avoids special casing later vs regime_el. */
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return get_phys_addr_disabled(env, address, access_type, mmu_idx,
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is_secure, result, fi);
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case ARMMMUIdx_Stage1_E0:
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case ARMMMUIdx_Stage1_E1:
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case ARMMMUIdx_Stage1_E1_PAN:
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/* First stage lookup uses second stage for ptw. */
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ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
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break;
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case ARMMMUIdx_E10_0:
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s1_mmu_idx = ARMMMUIdx_Stage1_E0;
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goto do_twostage;
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case ARMMMUIdx_E10_1:
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s1_mmu_idx = ARMMMUIdx_Stage1_E1;
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goto do_twostage;
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case ARMMMUIdx_E10_1_PAN:
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s1_mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
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do_twostage:
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/*
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* Call ourselves recursively to do the stage 1 and then stage 2
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* translations if mmu_idx is a two-stage regime, and EL2 present.
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@ -2522,6 +2553,12 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
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return get_phys_addr_twostage(env, ptw, address, access_type,
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result, fi);
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}
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/* fall through */
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default:
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/* Single stage and second stage uses physical for ptw. */
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ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS;
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break;
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}
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/*
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